PM7375-SC datasheet(40/430 Pages) PMC

40 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

AD[0]

AD[1]

AD[2]

AD[3]

AD[4]

AD[5]

AD[6]

AD[7]

AD[8]

AD[9]

AD[10]

AD[11]

AD[12]

AD[13]

AD[14]

AD[15]

AD[16]

AD[17]

AD[18]

AD[19]

AD[20]

AD[21]

AD[22]

AD[23]

AD[24]

AD[25]

AD[26]

AD[27]

AD[28]

AD[29]

AD[30]

AD[31]

I/O

208

205

204

203

The PCI address and data (AD[31:0]) bus is used to

carry multiplexed address and data. During the first

clock cycle of a transaction, AD[31:0] contains a

physical byte address. Subsequent clock cycles of a

transaction should contain data.

A transaction is defined as an address phase followed

by one or more data phases. When Little-Endian byte

formatting is used. AD[31:24] should contain the most

significant byte of a DWORD while AD[7:0] should

contain the least significant byte of a DWORD. When

Big-Endian byte formatting is used. AD[7:0] should

contain the most significant byte of a DWORD while

AD[31:24] should contain the least significant byte of a

DWORD.

When the LASAR-155 is the initiator, AD[31:0] are

outputs during the first (address) phase of a

transaction. For write transactions, AD[31:0] remain

outputs for the data phases of the transaction. For

read transactions, AD[31:0] become inputs.

When the LASAR-155 is the target, AD[31:0] are

inputs during the first (address) phase of a

transaction. For write transactions, AD[31:0] become

inputs for the data phases of the transaction. For read

transactions, AD[31:0] remain outputs for the

transaction.

When the LASAR-155 is not involved in the current

transaction, AD[31:0] are tri-stated.

Signals, AD[31:0] are updated on the rising edge of

PCICLK or sampled using the rising edge of PCICLK

depending on whether they are outputs or inputs.

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