PM7375-SC datasheet(63/430 Pages) PMC

63 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.3.2.1 Fig. 9.3 HEC Verification State Diagram

DETECTION

MODE

ATM DELINEATION

SYNC STATE

CORRECTION

MODE

No Errors Detected

In M Cells

(Pass M Cell)

Apparent Multi-Bit Error

(Drop Cell)

Errors

Detected

(Drop Cell)

No Errors

Detected

(Pass Cell)

ALPHA

consecutive

incorrect HCS's

(To HUNT state)

DELTA

consecutive

correct HCS's

(From PRESYNC

state)

Single-Bit Error

(Correct Error

and Pass Cell)

No Errors Detected

(Pass Cell)

In normal operation, the HEC verification state machine remains in the 'Correction

Mode' state. Incoming cells containing no HEC errors are passed for further

ATM/AAL layer processing. In addition, incoming cells with single-bit errors are

corrected and the resulting cells are passed for further ATM/AAL layer processing.

Upon detection of a single- bit error or a multi-bit error, the state machine transitions

to the 'Detection Mode' state. In this state, programmable HEC error filtering is

provided. The detection of any HEC error causes the corresponding cell to be

dropped. The state machine transitions back to the 'Correction Mode' state when M

(where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not

discarded.

Two 8-bit saturating one second HEC error event counters are provided to

accumulate correctable HEC errors and uncorrectable HEC errors. Counters are

enabled only when the RACP is in the SYNC state.

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