STAC9752 datasheet(36/95 Pages) IDT

36 / 95 page

STAC9752/9753

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

IDT™

STAC9752/9753

REV 3.3 1206

TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING

5.3.8.

Slot 12: Audio GPIO Control Channel

AC-Link output frame slot 12 contains the audio GPIO control outputs.

5.4.

AC-Link Input Frame (SDATA_IN)

The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data

targeting the AC‘97 Controller. As is the case for audio output frame, each AC-Link input frame con-

sists of 12 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are used

for AC-Link protocol infrastructure.

The following diagram illustrates the time slot-based AC-Link protocol.

Figure 17. STAC9752/9753 Audio Input Frame

A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to

the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97

CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97

CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit

position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the

AC‘97 Controller on the falling edge of BIT_CLK. This sequence ensures that data transitions and

subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 18. Start of an Audio Input Frame

SDATA_IN’s composite stream is MSB first with all non-valid bit positions (for assigned and/or unas-

signed time slots) stuffed with 0 by the AC‘97 CODEC. SDATA_IN data is sampled on the falling

edges of BIT_CLK.

SYNC

BIT_CLK

SDATA_IN

slot1

slot2

End of previous audio frame

slot(12)

"0"

Data Phase

20.8 uS (48 kHZ)

Tag Phase

12.288 MHz

Time Slot "Valid" Bits

Slot 1

Slot 2

Slot 3

Slot 12

("1" = time slot contains valid PCM data)

valid

"0"

Frame

"0"

SYNC

BIT_CLK

SDATA_ IN

slot1

slot2

End of previous audio frame

Codec

Ready

SYNC

detected

first

SDATA_OUT

bit of frame

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