PIC18F4685-ISLASHSP datasheet(151/484 Pages) MICROCHIP

151 / 484 page

Preliminary

DS39761B-page 149

PIC18F2682/2685/4682/4685

11.3

Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not directly readable or writable;

its value is set by the PSA and T0PS2:T0PS0 bits

(T0CON<3:0>)

which

determine

the

prescaler

assignment and prescale ratio.

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256 in power-of-2 increments are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0

, BSF TMR0, etc.) clear the prescaler count.

11.3.1

SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before re-

enabling the interrupt, the TMR0IF bit must be cleared

in software by the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1:

REGISTERS ASSOCIATED WITH TIMER0

Note:

Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

TMR0L

Timer0 Register Low Byte

TMR0H

Timer0 Register High Byte

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

TRISA

TRISA7(1)

TRISA6(1) PORTA Data Direction Register

Legend:

= unknown, u = unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.

Note 1:

RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

PIC18F4685-I/SP датащи(PDF) 151 Page - Microchip Technology

PIC18F4685-I/SP датащи(HTML) 151 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL