SZF2002 datasheet(30/76 Pages) PHILIPS

30 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

16.1

Serial Control Register (S1CON)

Table 23 Serial Control Register (SFR address D8H)

Table 24 Description of S1CON bits

76543210

CR2

ENS1

STA

STO

CR1

CR0

BIT

SYMBOL

DESCRIPTION

ENS1

Enable serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are

in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When

ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to

logic 1.

5STA

START ﬂag. When this bit is set in Slave mode, the SIO hardware checks the status of

the I2C-bus and generates a START condition if the bus is free or after the bus becomes

free. If STA is set while the SIO is in Master mode, SIO will generate a repeated START

condition.

4STO

STOP ﬂag. With this bit set while in Master mode a STOP condition is generated. When

a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO ﬂag.

STO may also be set in Slave mode in order to recover from an error condition. In this

case no STOP condition is transmitted to the I2C-bus. However, the SIO hardware

behaves as if a STOP condition has been received and releases the SDA and SCL

lines. The SIO then switches to the not addressed Slave receiver mode. The STOP ﬂag

is cleared by the hardware.

3SI

SIO interrupt ﬂag. This ﬂag is set and an interrupt is generated, after any of the

following events occur:

• A START condition is generated in Master mode

• Own slave address has been received during AA = 1

• The general call address has been received while GC (S1ADR.0) = 1 and AA = 1

• A data byte has been received or transmitted in Master mode (even if arbitration is lost)

• A data byte has been received or transmitted as selected slave

• A STOP or START condition is received as selected slave receiver or transmitter.

2AA

Assert Acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is

returned during the acknowledge clock pulse on the SCL line when:

• Own slave address is received

• General call address is received; GC (S1ADR.0) = 1

• A data byte is received while the device is programmed to be a Master receiver

• A data byte is received while the device is a selected Slave receiver.

When this bit is reset, no acknowledge is returned. Consequently, no interrupt is

requested when the own slave address or general call address is received.

CR2

Clock Rate selection. These 3 bits determine the serial clock frequency when SIO is in

the Master mode. See Table 25.

CR1

CR0

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