SZF2002 datasheet(25/76 Pages) PHILIPS

25 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

14 ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog input circuitry consists of a 6-input analog

multiplexer and an ADC with 8-bit resolution. The analog

supply (VDDA) and analog ground (VSSA) are connected via

separate input pins. For clock frequencies higher than

8 MHz the clock prescaler is needed (divide-by-2).

The functional diagram of the ADC is shown in Fig.14.

The ADC is controlled using the ADC Control Register

(ADCON). Input channels are selected by the analog

multiplexer via the ADCON register bits AADR0 to AADR2.

A conversion is started by setting the ADCS bit in the

ADCON register. The completion of the 8-bit ADC

conversion is flagged by ADCI in the ADCON register,

which will generate an interrupt if this is enabled (EAD).

The result is stored in the Special Function Register ADCH

(address C5H).

To save power the ADC current is switched on only during

conversion and is independent of the processor mode

(active, Idle or Power-down). If the processor goes into Idle

or Power-down mode, the ADC interrupt must be used to

wake-up the CPU again.

While ADCS = 1 or ADCI = 1, a new ADC start will be

blocked and consequently lost, however an ADC

conversion already in progress will finish uninterrupted.

An ADC conversion already in progress is aborted when

the Power-down mode is entered. The result of a

completed conversion (ADCI = 1) remains unaffected

when entering the Idle or Power-down mode.

When no result of a completed conversion (ADCI = 0) is

available, the ADCON and ADCH registers will be reset

when entering the Power-down mode. Note that AADRx

and CKDIV have to be set explicitly to restore their

previous values for the first conversion after Power-down

mode.

Table 14 Conversion time in clock cycles

CONDITION

MAX.

REMARK

fclk ≤ 8 MHz,

CKDIV = 0

288

normal conversion

fclk > 8 MHz,

CKDIV = 1

576

prescaler used

Fig.14 Functional diagram of analog input.

(1) For the descriptions of ADCON bits see Table 16.

handbook, full pagewidth

MGM187

ANALOG INPUT

MULTIPLEXER

8-BIT ADC

(succesive approximation)

ADCON

(1)

Power-down

DDA

SSA

ADCH

INTERNAL BUS

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

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