SZF2002 datasheet(27/76 Pages) PHILIPS

27 / 76 page

1998 Aug 26

Philips Semiconductors

Product speciﬁcation

Low voltage 8-bit microcontroller with

6-kbyte embedded RAM

SZF2002

15 REDUCED POWER MODES

There are two software selectable modes of reduced

activity for further power reduction: Idle and Power-down.

15.1

Idle mode

Idle mode operation permits the interrupt, serial ports,

timer blocks, PWM and ADC to continue to function while

the clock to the CPU is halted.

The following functions remain active during the Idle

mode:

• Timer 0, Timer 1, Timer 2 and Timer 3

(Watchdog Timer)

• UART, I2C-bus interface

• Internal interrupt

• External interrupt

• PWM

• ADC.

These functions may generate an interrupt or reset; thus

ending the Idle mode.

The instruction that sets bit IDL (PCON.0) is the last

instruction executed in the normal operating mode before

the Idle mode is activated. Once in Idle mode, the CPU

status is preserved along with the Stack Pointer, Program

Counter, Program Status Word, SFRs and Accumulator.

The RAM and all other registers maintain their data during

Idle mode. The status of the external pins during Idle mode

is shown in Table 20.

15.1.1

TERMINATION OF THE IDLE MODE USING AN

ENABLED INTERRUPT

Activation of any enabled interrupt will cause IDL

(PCON.0) to be cleared by hardware thus terminating the

Idle mode. The interrupt is serviced, and following the

RETI instruction, the next instruction to be executed will be

the one following the instruction that put the device in the

Idle mode. The flag bits GF0 (PCON.2) and GF1 (PCON.3)

may be used to determine whether the interrupt was

received during normal execution or during the Idle mode.

For example, the instruction that writes to PCON.0 can

also set or clear one or both flag bits. When the Idle mode

is terminated by an interrupt, the service routine can

examine the status of the flag bits.

15.1.2

TERMINATION OF THE IDLE MODE USING AN

EXTERNAL HARDWARE RESET

The second way of terminating the Idle mode is with an

external hardware reset, or an internal reset caused by an

overflow of Timer 3 (Watchdog Timer). Since the clock is

still running, the hardware reset is required to be active for

two machine cycles (12 clock periods) to complete the

reset operation. Reset redefines all SFRs but does not

affect the on-chip RAM.

15.2

Power-down mode

The Power-down operation freezes the SZF2002.

The Power-down mode can only be activated by setting

the PD bit in the PCON register.

The instruction that sets PD (PCON.1) is the last executed

prior to going into the Power-down mode. Once in the

Power-down mode, the internal clock is stopped.

The contents of the on-chip RAM and the SFRs are

preserved. The port pins output the value held by their

respective SFRs. OE is held HIGH, but CE is switched to

HIGH, so the external ROM will not be enabled during

power down, to save system power.

15.3

Wake-up from Power-down mode

Setting the PD flag in the PCON register forces the

controller into the Power-down mode. Setting this flag

enables the controller to be woken-up from the

Power-down mode with either the external interrupts

INT0 to INT8, or a reset operation. The wake-up operation

has two basic approaches as explained in

Section 15.3.1 and 15.3.2.

15.3.1

WAKE-UP USING INT0 TO INT8

If any of the interrupts INT0 to INT8 is enabled, the device

can be woken-up from the Power-down mode with these

external interrupts. The user must ensure that the external

clock is stable before the controller restarts, the internal

clock will remain inactive for 18 clock periods. This is

controlled by an on-chip delay counter.

15.3.2

WAKE-UP USING RST

To wake-up the SZF2002, the RST pin must be kept HIGH

for a minimum of 12 clock cycles. The user must ensure

that the external clock is stable before the controller

restarts (at RST falling edge), the internal clock will remain

inactive for 18 clock periods. This is controlled by an

on-chip delay counter.

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