XRT79L71IB datasheet(7/109 Pages) EXAR

7 / 109 page

XRT79L71

III

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

TABLE 17: TIMING INFORMATION FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ..................................................... 96

FIGURE 21. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1 ACCESS) .................................... 98

FIGURE 22. TIMING DIAGRAM FOR THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 2 ACCESS) .................................... 98

RECEIVE PAYLOAD DATA OUTPUT INTERFACE ....................................................... 99

RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................... 99

TABLE 18: TIMING INFORMATION FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK ...................................................... 99

FIGURE 23. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (SERIAL MODE).............................................. 99

FIGURE 24. TIMING DIAGRAM FOR THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE (NIBBLE-PARALLEL MODE) ........................... 100

RECEIVE OVERHEAD DATA OUTPUT INTERFACE .................................................. 101

RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS .............................. 101

AC ELECTRICAL CHARACTERISTICS (CONT.)............................................................................................... 101

FIGURE 25. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 1 - USING RXOHCLK) ................ 102

FIGURE 26. TIMING DIAGRAM FOR THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE (METHOD 2 - USING RXOHENABLE) .......... 102

RECEIVE UTOPIA INTERFACE .................................................................................... 103

RECEIVE UTOPIA INTERFACE ............................................................................................................. 103

FIGURE 27. TIMING DIAGRAM FOR THE RECEIVE UTOPIA INTERFACE BLOCK ................................................................................ 103

TABLE 19: TIMING INFORMATION FOR THE RECEIVE UTOPIA INTERFACE BLOCK ........................................................................... 103

12.0 ARCHITECTURAL/FUNCTIONAL DESCRIPTION OF THE XRT79L71 1-CHANNEL DS3/E3 ATM UNI/

PPP/CLEAR-CHANNEL FRAMER WITH LIU IC - CLEAR CHANNEL FRAMER AND HIGH-SPEED HDLC

CONTROLLER MODE APPLICATIONS (SEE 79L71-CC-ARC-DESC.PDF) .................................... 104

13.0 ARCHITECTURAL DESCRIPTION OF THE XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-

CHANNEL FRAMER WITH LIU IC - ATM UNI APPLICATIONS (SEE 79L71-ATM-ARC-DESC.PDF) 104

14.0 ARCHITECTURAL DESCRIPTION OF THE XRT79L71 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-

CHANNEL FRAMER WITH LIU IC - POS-PHY/PPP APPLICATIONS (SEE 79L71-PPP-ARC-DESC.PDF)

104

ORDERING INFORMATION .......................................................................................... 105

PACKAGE DIMENSIONS .............................................................................................. 105

208 SHRINK THIN BALL GRID ARRAY (17.0 MM X 17.0 MM, STBGA) ............................................... 105

REVISION HISTORY .................................................................................................................................... 106

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