XRT79L71IB datasheet(27/109 Pages) EXAR

27 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

A10

TxCellTxed/

TxNibFrame/

ValidFCS

Transmit ATM Cell Generator indicator/Transmit Nibble Frame Indicator/

Valid FCS Indicator output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM Mode, the Clear-Channel Framer Mode or in

the High-Speed HDLC Controller Mode.

ATM Mode - TxCellTxed TxCellTxed - Transmit ATM Cell Generator Indica-

tor:

This output pin pulses "High" (for one TxInClk or RxOutClk period) each time the

ATM Transmit Cell Processor block transmits an ATM cell to either the Transmit

PLCP Processor or the Transmit DS3/E3 Framer block.

Clear-Channel Framer Mode - TxNibFrame - Transmit Nibble Frame Indica-

tor Output pin:

This output pin pulses "High" when the last nibble of a given DS3 or E3 frame is

expected at the TxNib[3:0] input pins.

The purpose of this output pin is to alert the System-Side terminal equipment

that it needs to begin the transmission of a new DS3 or E3 frame to the

XRT79L71.

NOTE: This output pin is not active if the XRT79L71 is configured to operate in

the Serial-Mode.

High-Speed HDLC Controller Mode - ValidFCS:

The combination of the RxIdle and ValidFCS output signals are used to convey

information about data that is being output via the Receive High-Speed HDLC

Controller Output Interface - Data bus output (RxHDLCDat_[7:0]).

If RxIdle = "High":

The Receive High-Speed HDLC Controller Output Interface block with drive this

output pin "High" anytime the flag sequence octet (0x7E) is present on the RxH-

DLCDat[7:0] output data bus.

If RxIdle and ValidFCS are both "High":

The Receive High-Speed HDLC Controller Output Interface block has received a

complete HDLC frame, and has determined that the FCS value within this HDLC

frame are valid.

If RxIdle is "High" and ValidFCS is "Low":

The Receive High-Speed HDLC Controller Output Interface block has received a

complete HDLC frame, and has determined that the FCS value within this HDLC

frame is invalid.

If RxIdle is "Low" and ValidFCS is "High":

The Receive High-Speed HDLC Controller Output Interface block has received

an ABORT sequence.

NOTE: This input pin is active if the XRT79L71 has been configured to operate in

the PPP Mode.

PIN #NAME

TYPE

DESCRIPTION

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