XRT79L71IB datasheet(2/109 Pages) EXAR

2 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

• Supports ATM cell payload scrambling

• Maps ATM cells into E3 or DS3 frame

• PLCP frame and mapping of ATM cell streams

RECEIVE CELL PROCESSING

• Extraction of ATM cells from PLCP frame or directly

from E3 or DS3 frame

• Termination of PLCP frame

• Supports payload cell de-scrambling

TRANSMIT PACKET PROCESSING

• Inserts PPP packets into data stream

• Maps HDLC data stream directly into DS3 or E3

frame

• Extracts in-band messaging packets

• Supports CRC-16/32, HDLC flag and Idle

sequence generation

RECEIVE PACKET PROCESSING

• Extracts HDLC data stream from DS3 or E3 frame

• Inserts in-band messaging packets

• Detects and removes HDLC flags

UTOPIA/ SYSTEM INTERFACE

• 8/16 bit UTOPIA Level I and II and PPP Multi-PHY

Interface operating at 25, 33 or 50 MHz.

• Compliant with ATM Forum UTOPIA II interface

• Programmable FIFO size for both Transmit and

Receive direction

• Compliant to POS-PHY Level 2 interface

SERIAL INTERFACE

• Serial clock and data interface for accessing DS3/

E3 framer

• Serial clock and data interface for accessing cell/

packet processor

APPLICATIONS

• Digital Access and Cross Connect Systems

• 3G Base Stations

• DSLAMs

• Digital, ATM, WAN and LAN Switches

FIGURE 1. BLOCK DIAGRAM OF THE XRT79L71

TU-3

POH

Processor

Jitter

Attenuator

Rx DS3/

Fram er

PLCP &

Overhead

UTOPIA/

POS-PHY

Interface

HDLC

Controller

Receiver Block

JTAG Test Port

Clock &

Data

Recov ery

AGC/

Equalizer

RTIP

RRING

Transm itter Block

ATM Cell

Processor

or PPP

Processor

UTOPIA/

POS-PHY

Interface

ATM Cell

Processor

or PPP

Processor

HDLC

Controller

PLCP &

Overhead

Tx DS3/

Fram er

Jitter

Attenuator

Tim ing

Control

Pulse

Shaper

TTIP

TRING

Microprocessor Interface

12.288

MHz

ClkIN

Clock

Synthesizer

E3CLK

DS3CLK

Receive

Utopia

POS-PHY

Interface

Transm it

Utopia

POS-PHY

Interface

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