XRT79L71IB datasheet(49/109 Pages) EXAR

49 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

RxTSX/

RxPSOF

Receive - Change of Port Indicator Output/Receive - Start of PPP Packet in

Chunk Mode:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Packet Mode or Cell-Chunk Mode.

Packet Mode - RxTSX - Receive POS-PHY Interface - Change of Port Indi-

cator Output (POS-PHY Level 3, Packet Mode Only):

The XRT79L71 pulses this output pin "High" when an in-band port address is

present on the RxPData[15:11] output pins.

When this output pin is "High", the value of RxPData[15:11] is the address value

of the RxFIFO to be selected. This is an indication (to the Link Layer Proces-

sor) that subsequent read operations, from RxPData[15:0] will be from the

RxFIFO (or Receive POS-PHY Port) corresponding to this particular in-band

address.

NOTE:

In order to avoid Receive POS-PHY Interface bus contentions, we

advise that the user avoid configuring the XRT79L71 in the POS-PHY

Level 3 Mode.

Chunk Mode - RxPSOF - Receive Start of Packet Output Indicator:

The XRT79L71 pulses this output pin "High" in order to indicate that the first

byte (or word) of a given Packet is placed on the RxPData[15:0] pins.

NOTE: This output pin is only active if the XRT79L71 has been configured to

operate in the POS-PHY Level 3, Packet Mode or in the Chunk Mode.

RxUEN/

RxPEN

Receive UTOPIA Interface - Output Enable/Receive POS-PHY Interface -

Output Enable:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM UNI or PPP mode.

ATM UNI Mode - RxUEN - Receive UTOPIA Interface - Read/Output Enable

Input pin:

This active-"Low" input signal is used to control the drivers of the Receive UTO-

PIA Data Bus. When this signal is "High" (negated) then the Receive UTOPIA

Data Bus is tri-stated. When this signal is asserted (e.g., pulled to a logic "Low"

level), then the contents of the byte or word that is at the front of the RxFIFO will

be popped and placed on the Receive UTOPIA Data bus on the very next rising

edge of RxUClk.

PPP Mode - RxPEN - Receive POS-PHY Interface - Read/Output Enable

Input pin:

This active-"Low" input signal is used to control the drivers of the Receive POS-

PHY Data Bus. When this signal is "High" (negated) then the Receive POS-

PHY Data Bus is tri-stated. When this signal is asserted, then the contents of

the byte or word that is at the front of the RxFIFO will be popped and placed on

the Receive POS-PHY Data bus on the very next rising edge of RxPClk.

NOTE: The user should tie these input pins to GND, to operate the XRT79L71

in either the Clear-Channel Framer or High-Speed HDLC Controller

Modes.

PIN #NAME

TYPE

DESCRIPTION

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