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TMD3721 датащи(PDF) 51 Page - OSRAM GmbH |
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TMD3721 датащи(HTML) 51 Page - OSRAM GmbH |
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51 / 89 page ![]() Page 50 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Register O ver view PWM_PRD_H Register (Address 0xB6) Figure 67: PWM_PRD_H Register PWM_PRD register stores the last PWM period. This is 14bit divided into 2 registers {PWM_PRD_H, PWM_PRD_L} with resolution of 1.357μs/bit. PWM_HIP_L (Address 0xB7) Figure 68: PWM_HIP_L PWM_HIP_H (Address 0xB8) Figure 69: PWM_HIP_H PWM_HIP register stores the last PWM high period. This is 14bit divided into 2 registers {PWM_HIP_H, PWM_HIP_L} with resolution of 1.357μs/bit. It is recommended that PWM signal is in the frequency range of 45Hz to 10KHz with minimum active pulse length 16μs. Addr: 0xB6 PWM_PRD_H Bit Bit Name Default Access Bit Description 7:6 Reserved 00 R Reserved. Must be set to default value. 5:0 PWM_PRD_H 000000 R The upper 6 bits of the 14-bit PWM period data Addr: 0xB7 PWM_HIP_L Bit Bit Name Default Access Bit Description 7:0 PWM_HIP_L 0x00 R The low byte of the 14-bit PWM signal high period data. Addr: 0xB8 PWM_HIP_H Bit Bit Name Default Access Bit Description 7:6 Reserved 00 R Reserved. Must be set to default value. 5:0 PWM_HIP_H 000000 R The upper 6 bits of the 14-bit PWM signal high period data. |
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