TMD3721 datasheet(50/89 Pages) OSRAM

50 / 89 page

Datasheet, Public

Page 49

[v3-00] 2023-May-26

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TMD3721 − Register Overview

VSYNC_PRD_L Register (Address 0xB2)

Figure 64:

VSYNC_PRD_L Register

VSYNC_PRD_H Register (Address 0xB3)

Figure 65:

VSYNC_PRD_H Register

VSYNC_PRD stores the last VSYNC signal period. This is 16-bit

divided into 2 registers {VSYNC_PRD_H, VSYNC_PRD_L} with

resolution of 1.357μs/bit. It is recommended that VSYNC signal

is in the frequency range of 11.25Hz to 1KHz with minimum

active pulse width 16μs, although the counter is able to detect

a much higher frequency. Once external VSYNC signal is lost,

VSYNC_LOST_INT interrupt is generated if VSIEN =1. Then

software has option to enable internal VSYNC by enabling INT_

VSYNC_EN. The internal VSYNC will generate with frequency of

last period stored in VSYNC_PRD registers. Users can write

VSYNC_PRD registers for a desired frequency before enabling

the internal VSYNC feature. Once the device detects external

VSYNC signal, the INT_VSYNC_EN bit will be cleared

automatically, VSYNC_PRD value will update according to the

period detected.

PWM_PRD_L Register (Address 0xB5)

Figure 66:

PWM_PRD_L Register

Addr: 0xB2

VSYNC_PRD_L

Bit

Bit Name

Default

Access

Bit Description

7:0

VSYNC_PRD_L

0x00

The low byte of the 16-bit VSYNC period data.

Addr: 0xB3

VSYNC_PRD_H

Bit

Bit Name

Default

Access

Bit Description

7:0

VSYNC_PRD_H

0x00

The high byte of the 16-bit VSYNC period data.

Addr: 0xB5

PWM_PRD_L

Bit

Bit Name

Default

Access

Bit Description

7:0

PWM_PRD_L

0x00

The low byte of the 14-bit PWM period data.

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