TMD3721 datasheet(28/89 Pages) OSRAM

28 / 89 page

Datasheet, Public

Page 27

[v3-00] 2023-May-26

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TMD3721 − Register Overview

PTIME Register (Address 0x82)

Figure 29:

PTIME Register

AILTL Register (Address 0x84)

Figure 30:

AILTL Register

AILTH Register (Address 0x85)

Figure 31:

AILTH Register

The ALS clear channel is compared against low-going 16-bit

threshold value set by AILTL and AILTH. The contents of the

AILTH and AILTL registers are combined and treated as a

sixteen-bit threshold value. If the value generated by the ALS

clear channel is below the AILTL/H threshold and the APERS

value is reached, the AINT bit is asserted. If AIEN is set, then the

INT pin will also assert.

When setting the 16-bit ALS threshold AILTL must be written

first, immediately followed by AILTH. Internally, the lower 8 bits

are buffered until the upper 8 bits are written. As the upper

8 bits are written both the high and low bytes are

simultaneously latched as a 16-bit value.

When residue bits are enabled by ENAB_RES_BITS, the data

format for AILT should be U13.3 and when residue bits are not

required, it should be U16.0.

Addr: 0x82

PTIME

Bit

Bit Name

Default

Access

Bit Description

7:0

PTIME

0x1F

This register defines the duration of 1 Prox Sample,

which is (PTIME + 1)*88μs. PTIME needs to be

programmed greater than proximity integration time,

otherwise it's ignored.

Addr: 0x84

AILTL

Bit

Bit Name

Default

Access

Bit Description

7:0

AILTL

0x00

This register sets the low byte of the LOW ALS threshold.

Addr: 0x85

AILTH

Bit

Bit Name

Default

Access

Bit Description

7:0

AILTH

0x00

This register sets the high byte of the LOW ALS threshold.

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