TMD3721 datasheet(29/89 Pages) OSRAM

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[v3-00] 2023-May-26

TMD3721 − Register O ver view

When DOUBLE_DATA_MODE is used, the data AILTH register

should be 0, only the data AILTL register is used. The data format

when residue bits are enabled is U7.1. When residue bits are

disabled, the data format should be U8.0.

AIHTL Register (Address 0x86)

Figure 32:

AIHTL Register

AIHTH Register (Address 0x87)

Figure 33:

AIHTH Register

The ALS clear channel is compared against high-going 16-bit

threshold value set by AIHTL and AIHTH. The contents of the

AIHTH and AIHTL registers are combined and treated as a

sixteen-bit threshold value. If the value generated by the ALS

clear channel is above the AIHTL/H threshold and the APERS

value is reached, the AINT bit is asserted. If AIEN is set, then the

INT pin will also assert.

When setting the 16-bit ALS threshold AIHTL must be written

first, immediately followed by AIHTH. Internally, the lower 8 bits

are buffered until the upper 8 bits are written. As the upper 8

bits are written both the high and low bytes are simultaneously

latched as a 16-bit value.

When residue bits are enabled by ENAB_RES_BITS, the data

format for AIHT should be U13.3 and when residue bits are not

required, it should be U16.0

When DOUBLE_DATA_MODE is used, the data AIHTH register

should be 0, only the data AIHTL register is used. The data

format when residue bits are enabled is U7.1. When residue bits

are disabled, the data format should be U8.0

Addr: 0x86

AIHTL

Bit

Bit Name

Default

Access

Bit Description

7:0

AIHTL

0x00

This register sets the low byte of the HIGH ALS threshold.

Addr: 0x87

AIHTH

Bit

Bit Name

Default

Access

Bit Description

7:0

AIHTH

0x00

This register sets the high byte of the HIGH ALS threshold.

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