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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMD3721 датащи(PDF) 62 Page - OSRAM GmbH |
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TMD3721 датащи(HTML) 62 Page - OSRAM GmbH |
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62 / 89 page  Datasheet, Public Page 61 [v3-00] 2023-May-26 Document Feedback TMD3721 − Register Overview Although ASP1, ASP2, ATIME are programmed with high flexibility, it always recommend to program ATIME to be an integer multiple of ASP1+ASP2. Explained by a formula: ATIME =N x(ASP1 +ASP2), where N is a positive integer. ATIME Register (Address 0xE6) Figure 86: ATIME Register The ATIME register controls the integration time of the ALS ADCs. The timer is implemented with a down counter with 0x00 as the terminal count. The timer is clocked at a 2.779ms nominal rate. Loading 0x00 will generate a 2.779ms integration time, loading 0x01 will generate a 5.558ms integration time, and so forth. By default, ALS data are sampled and stored in FIFO registers by every ATIME period. If enable ASP1 ASP2, ALS data sampling period is defined by ASP1 ASP2. Addr: 0xE6 ATIME Bit Bit Name Default Access Bit Description 7:0 ATIME 0x00 RW The ATIME value specifies the ALS integration time in 2.779ms intervals. 0x00 indicates 2.779ms. The maximum ALS count value depends on the integration time. For every 2.779ms, the maximum value increases by 2048. This means that to be able to reach ALS full scale, the integration time has to be at least 32*2.779ms. Value Integration Cycles Integration Time Maximum ALS Value 0x00 1 2.779ms 2047 0x01 2 5.558ms 4095 0x02 3 8.336 6143 …… … … 0x1F 32 88.923ms 65535 …… … … 0xFF 256 711.381ms 65535 |
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