TMD3721 datasheet(68/89 Pages) OSRAM

68 / 89 page

Datasheet, Public

Page 67

[v3-00] 2023-May-26

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TMD3721 − Register Overview

FIFO_CONTROL Register (Address 0xF1)

Figure 93:

FIFO_CONTROL Register

Addr: 0xF1

FIFO_CONTROL

Bit

Bit Name

Default

Access

Bit Description

Reserved

Reserved. Must be set to default value.

FIFO_LVL_LSB

Contains the LSB of FIFO_LVL when DOUBLE_DATA_

MODE is used.

See FIFO_LVL for details.

5:3

FIFO_THR_LVL

000

FIFO level threshold. When FIFO_LVL is greater than or

equal to FIFO_THR_LVL, FTINT flag is set, and an interrupt

is generated if FTIEN is enabled.

Value

FIFO Level Threshold

No intermediate levels to generate

interrupt. Full FIFO is available.

16 (32 when DOUBLE_DATA_MODE=1)

32 (64 when DOUBLE_DATA_MODE=1)

48 (96 when DOUBLE_DATA_MODE=1)

64 (128 when DOUBLE_DATA_MODE=1)

80 (160 when DOUBLE_DATA_MODE=1)

96 (192 when DOUBLE_DATA_MODE=1)

112 (224 when DOUBLE_DATA_MODE=1)

2FIFO_CLR

When this bit is set, the FIFO is cleared, the read and write

pointers are reset to 0, any read from FIFO will return 0.

It has to be noted that FIFO_CLR doesn't clear FIFO_OVF

flag if it's set. It requires a dummy read to FIFO data

before or after FIFO_CLR command to clear FIFO_OVF

flag.

This bit needs to be set when ALS is disabled.

FIFO_EMPTY

Indicates that the FIFO is empty.

When FIFO is empty, data read from FIFO returns 0.

FIFO_OVF

Indicates that the FIFO is full.

When FIFO is full, no new data is written into the FIFO.

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