PCA5007 datasheet(21/112 Pages) PHILIPS

21 / 112 page

1998 Oct 07

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

6.8.2

SERIAL CONTROL REGISTER (S1CON)

Table 7

Serial Control Register (S1CON, SFR address D8H)

Table 8

Description of the S1CON bits

6.8.3

DATA SHIFT REGISTER (S1DAT)

S1DAT contains the serial data to be transmitted or data which has just been received. Bit 7 is transmitted or received

first; i.e. data shifted from left to right.

Table 9

Data Shift Register (S1DAT, SFR address DAH)

6.8.4

ADDRESS REGISTER (S1ADR)

The slave address register is not available since slave mode is not supported.

6.8.5

SERIAL STATUS REGISTER (S1STA)

The contents of this register may be used as a vector to a service routine. This optimizes the response time of the

software and consequently that of the I2C-bus. S1STA is a read-only register. The status codes for all available modes

of a single master I2C-bus interface are given in Tables 12 to 14.

76543210

−

ENS1

STA

STO

−−

BIT

SYMBOL

FUNCTION

S1CON.7

−

CR2 is not available.

S1CON.6

ENS1

Enable Serial I/O. When ENS1 = 0, the serial I/O is disabled. SDA and SCL outputs are

in the high-impedance state; P1.6 and P1.7 function as open-drain ports. When

ENS1 = 1, the serial I/O is enabled. Output port latches P1.6 and P1.7 must be set to

logic 1.

S1CON.5

STA

START ﬂag. If STA is set while the SIO is in master mode, SIO will generate a repeated

START condition.

S1CON.4

STO

STOP ﬂag. With this bit set while in master mode a STOP condition is generated. When

a STOP condition is detected on the I2C-bus, the SIO hardware clears the STO ﬂag.

S1CON.3

SIO interrupt ﬂag. This ﬂag is set, and an interrupt is generated, after any of the

following events occur:

• A START condition is generated in master mode

• A data byte has been received or transmitted in master mode (even if arbitration is lost).

If this ﬂag is set, the I2C-bus is halted (by pulling down SCL). Received data is only valid

until this ﬂag is reset.

S1CON.2

Assert Acknowledge. When this bit is set, an acknowledge (LOW level to SDA) is

returned during the acknowledge clock pulse on the SCL line when:

• A data byte is received while the device is programmed to be a master receiver.

When this bit is reset, no acknowledge is returned.

S1CON.1

−

CR1 and CR0 are not available.

S1CON.0

−

76543210

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