PCA5007 datasheet(42/112 Pages) PHILIPS

42 / 112 page

1998 Oct 07

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

Table 35 Description of the WDCON bits

BIT

SYMBOL

FUNCTION

WDCON.7

COND

Load condition. Control signal from processor.

WDCON.6

WD3

WD0 to WD3 is the preset value for the high nibble of the watchdog timer. The value is

the number of seconds to expiry of the watchdog.

WDCON.5

WD2

WDCON.4

WD1

WDCON.3

WD0

WDCON.2

−

unused

WDCON.1

−

unused

WDCON.0

Load watchdog timer with WD0 to WD3. Control signal from processor.

6.16.3

SAMPLE SEQUENCE TO RELOAD THE WATCHDOG

The sequence to reload the watchdog with 1 s is:

MOV WDCON, #80H; prepare condition.

MOV WDCON, #01H; reload the timer.

6.17

2 or 4-FSK demodulator, ﬁlter and clock

recovery circuit

6.17.1

FUNCTION

The aim of the demodulator and clock recovery circuitry is

to take the signal from the receiver, to format it into

symbols and to transfer it to the processor. The two blocks

use the 76.8 kHz clock.

The demodulator decodes the incoming signal and

generates a sequence of NRZ data. This data is fed to the

clock recovery block which regenerates the

synchronization clock. This clock is used to sample and to

shift the symbols into register DMD3.

6.17.1.1

Demodulator and ﬁlter

The demodulator can operate both with 2-FSK and 4-FSK

(selected by the LEV bit). For both types of input signals

the so called demodulator, filter and direct modes are

allowed. The operational mode is selected on the basis of

the M bit and BF bit.

In the demodulator mode (M = 0 and BF = X) the I and Q

signals are decoded according to Table 36.

Operating in this mode, an offset compensation can be

performed and the calculated offset value is stored into

used by the processor to adjust the analog AFC output

voltage.

The offset coding is given in Table 37.

Both the filter and direct modes are intended for

applications with an external demodulator. In this case, at

the I and Q pins, there are fed NRZ data. In the 4-FSK

situation the MSB is at pin I and the LSB is at pin Q. In the

2-FSK situation, only pin I is used; pin Q must be

connected to VSS. In these two modes, the offset

calculation and compensation cannot be performed.

In the filter mode (M = 1 and BF = 0), the data is filtered

and then sent to the clock recovery. In the direct mode

(M = 1 and BF = 1), no function of the demodulator is

performed. Consequently there is no filtering on the data

which is sent directly to the clock recovery.

Table 36 Modulation coding

FREQUENCY

(Hz)

2-FSK

4-FSK

+4800

+1600

−1600

−4800

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