PCA5007 datasheet(56/112 Pages) PHILIPS

56 / 112 page

1998 Oct 07

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

Each of these events first starts the DC/DC converter to

ramp up VDD to 2.2 V. After an initial reset, generated by

the DC/DC converter when VDD is again at normal level, all

2 V blocks will restart their operation. The first instruction

will be fetched from address 0.

The edge sensitive interrupts (minute and wake-up) from

the internal sources will have been lost during restart and

must be polled from their SFRs. Events from P1 pins can

be served after enabling the interrupts, since they are level

sensitive.

6.20.4

STATUS OF EXTERNAL PINS

The status of the external pins during Idle and power-down

mode is shown in Table 51.

Table 51 Status of external pins during normal, Idle and power-down modes

6.20.5

POWER CONTROL REGISTER (PCON)

The reduced power modes are activated by software using this special function register. PCON is not bit addressable.

Table 52 Power Control Register (PCON and SFR address 87H)

Table 53 Power Control Register (PCON, SFR address 87H)

Notes

1. If logic 1s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (00000000).

2. This device does not support external XRAM access. Therefore the XRE bit is meaningless and should never be

written to logic 1.

MODE

MEMORY

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Normal

internal

port data

Idle

internal

port data

external

pull-up HIGH

port data

address

port data

Power-down

internal

pull-up HIGH

port data

external

pull-up HIGH

port data

address

port data

76543210

SMOD

XRE

ENIS

−

GF1

GF0

IDL

BIT

SYMBOL

FUNCTION

PCON.7

SMOD

Control bit to double data rate of UART, when set to logic 1.

PCON.6

XRE

If set to logic 1 enables external XRAM from address 0 on, if set to logic 0 the ﬁrst

768 XRAM bytes are in internal XRAM, the higher addresses come from external

XRAM; see note 2.

PCON.5

ENIS

Enable ISYNC. If bit is set, ISYNC can be monitored at pin EA in internal access mode.

The binary value of ISYNC changes each time a new instruction is fetched from

memory. This bit must not be set to logic 1 by user program!

PCON.4

−

reserved

PCON.3

GF1

General purpose ﬂag bit.

PCON.2

GF0

General purpose ﬂag bit.

PCON.1

Power-down bit. Setting this bit activates the power-down mode; see note 1.

PCON.0

IDL

Idle mode bit. Setting this bit activates the Idle mode; see note 1.

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