PCA5007 datasheet(6/112 Pages) PHILIPS

6 / 112 page

1998 Oct 07

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

PINNING

SYMBOL

TYPE

DESCRIPTION

P3.4 and P3.5

1 and 2

I/O

Port 3: P3.4 and P3.5 are conﬁgured as push-pull output only (option 3R; see

Section 6.6). Using the software input commands or the secondary port

function is possible by driving the port 3 output lines accordingly:

P3.4 secondary function: T0 (counter input for T0)

P3.5 secondary function: T1 (counter input for T1)

Beeper high volume control output. Used to drive external bipolar transistor.

P2.0 to P2.7

4 to 11

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups (option 1S;

see Section 6.6.3). As inputs, port 2 pins that are externally pulled LOW will

source current because of the internal pull-ups. (see Chapter “DC

characteristics”: Ipu). Port 2 emits the high-order address byte during fetches

from external program memory. In this application, it uses strong internal

pull-ups when emitting logic 1s. Port 2 is also used to control the parallel

programming mode of the on-chip OTP.

P0.0 to P0.4

12 to 16

I/O

Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1S; see

Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled HIGH by

the internal pull-ups and can be used as inputs. Port 0 is also the multiplexed

low-order address and data bus during access to external program and data

memory. In this application, it uses strong internal pull-ups when emitting 1s.

Port 0 also outputs the code bytes during OTP programming veriﬁcation.

VDDA

supply voltage for the analog parts of the PCA5007 and the

receiver/synthesizer control signals (Port 0 pins)

AFCOUT

Buffered analog output of DAC for automatic receiver frequency control.

A voltage proportional to the offset of the receiver frequency can be generated.

Can be enabled/disabled by software.

I(D1)

input from receiver: may be demodulated NRZ signal or Zero-IF. In phase

limited signal

Q(D0)

input from receiver: may be demodulated NRZ signal or Zero-IF, Quadrature

limited signal.

VSSA

ground signal reference (for the analog parts) (connected to substrate)

P0.5 to P0.7

22 to 24

I/O

Port 0: Port 0 is a bidirectional I/O port with internal pull-ups (option 1R,1R and

1S; see Section 6.6.3). Port 0 pins that have logic 1s written to them are pulled

HIGH by the internal pull-ups and can be used as inputs. Port 0 is also the

multiplexed low-order address and data bus during access to external program

and data memory. In this application, it uses strong internal pull-ups when

emitting 1s. Port 0 also outputs the code bytes during OTP programming

veriﬁcation.

P1.0 to P1.2

25 to 27

I/O

Port 1: Port 1 is an 8-bit quasi bidirectional I/O port with internal pull-ups.

Port 1 pins that have logic 1s written to them are pulled HIGH by the internal

pull-ups and can be used as inputs. As inputs, port 1 pins that are externally

pulled LOW will source current because of the internal pull-ups (see

Chapter “DC characteristics”: Ipu). P1.0 to P1.2 have external interrupts INT2 to

INT4 assigned.

P1.3

I/O

If the UART is disabled (ENS1 in S1CON.4 = 0) then P1.3 can be used as

general purpose P1 port pin. If the UART function is required, then a logic 1

must be written to P1.3. This I/O then becomes the RXD/data line of the UART.

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