PCA5007 datasheet(101/112 Pages) PHILIPS

101 / 112 page

1998 Oct 07

101

Philips Semiconductors

Product speciﬁcation

Pager baseband controller

PCA5007

15.4

Address space

The PCA5007 has a 20 kbytes memory and therefore 15 address pins. Applying an address above 32 kbytes

(address<15> = 1) leads to the selection of the extra rows. The user should not apply these addresses during

programming.

15.5

Single byte programming

Programming and verifying is shown in Fig.65. The upper and lower address byte are loaded one after the other.

The address latch control signals select the proper latch and the RdStrb signal opens the latch (level sensitive).

The order of loading the latches is not important. The data is latched if write enable bar becomes active. After

programming a byte, this byte can be verified without reloading the addresses. If more bytes are programmed after each

other having the same upper address, it is not necessary to reload this upper address.

15.6

Multiple byte programming

A multiple byte programming mode has been implemented to increase programming speed. In this mode four bytes can

be programmed in parallel. The addresses of these four bytes have to be equal except for bit 0 and bit 1. Loading the

address and data latches is enabled by making PGM HIGH and GBMbpB LOW at the same time. Figure 66 shows the

address and data set-up and the program pulse. Loading the upper address is only necessary if it differs from the upper

address of the previous quadruple of bytes. In this mode the data latches are controlled by the RdStrb signal (level

sensitive). Figure 67 shows the verification in this mode. It should be noted that data 3 is verified before data 0. If this is

unwanted the lower address byte of data 0 has to be loaded before verifying data 0 and the lower address byte of data 1

before verifying data 1.

Fig.65 Single byte programming mode.

handbook, full pagewidth

MGR168

VPP

P0.0 to P0.7

P2.1/LS1

P2.0/LS0

P2.2/PGM

P2.3/RdStrb

P2.5/WEB

P2.4/GBMbpB

Addr high

Addr low

Data in

Data out

Addr/data set-up

program

100

µs

verify

VDD = 12.5 to 13 V

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