AM29LV640MH datasheet(14/62 Pages) AMD

14 / 62 page

Am29LV640MH/L

December 14, 2005

DA TA SH EET

at V

HH for operations other than accelerated program-

ming, or device damage may result. In addition, no ex-

ternal pullup is necessary since the WP#/ACC pin has

internal pullup to V

CC.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

IO ± 0.3 V.

(Note that this is a more restricted voltage range than

IH.) If CE# and RESET# are held at VIH, but not within

IO ± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t

CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Refer to the DC Characteristics table for the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC +

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the DC Characteristics table for the automatic

sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at VSS±0.3 V, the device

draws CMOS standby current (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 16 for the timing diagram.

Output Disable Mode

When the OE# input is at V

IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

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