AM29LV640MH datasheet(36/62 Pages) AMD

36 / 62 page

Am29LV640MH/L

December 14, 2005

DA TA SH EET

Table 9.

Command Definitions (x8 Mode, BYTE# = V

IL)

Command

Sequence

(Note 1)

Bus Cycles (Notes 2–5)

First

Second

Third

Fourth

Fifth

Sixth

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (Note 6)

Reset (Note 7)

XXX

Manufacturer ID

AAA

555

AAA

X00

Device ID (Note 9)

AAA

555

AAA

X02

X1C

X1E

SecSi

™ Sector Factory Protect

(Note 10)

AAA

555

AAA

X06

(Note 10)

Sector Group Protect Verify

(Note 11)

AAA

555

AAA

(SA)X04

00/01

Enter SecSi Sector Region

AAA

555

AAA

Exit SecSi Sector Region

AAA

555

AAA

XXX

Program

AAA

555

AAA

Write to Buffer (Note 12)

AAA

555

WBL

Program Buffer to Flash

Write to Buffer Abort Reset (Note 13)

AAA

555

AAA

Unlock Bypass

AAA

555

AAA

Unlock Bypass Program (Note 14)

XXX

Unlock Bypass Reset (Note 15)

XXX

Chip Erase

AAA

555

AAA

555

AAA

Sector Erase

AAA

555

AAA

555

Program/Erase Suspend (Note 16)

XXX

Program/Erase Resume (Note 17)

XXX

CFI Query (Note 18)

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address . Addresses latch on falling edge of WE# or

CE# pulse, whichever happens later.

PD = Program Data for location PA. Data latches on rising edge of

WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A21–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within same write

buffer page as PA.

BC = Byte Count. Number of write buffer locations to load minus 1.

Notes:

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Shaded cells indicate read cycles. All others are write cycles.

4. During unlock and command cycles, when lower address bits are

555 or AAA as shown in table, address bits above A11 are don’t

care.

5. Unless otherwise noted, address bits A21–A11 are don’t cares.

6. No unlock or command cycles required when device is in read

mode.

7. Reset command is required to return to read mode (or to

erase-suspend-read mode if previously in Erase Suspend) when

device is in autoselect mode, or if DQ5 goes high while device is

providing status information.

8. Fourth cycle of autoselect command sequence is a read cycle.

Data bits DQ15–DQ8 are don’t care. See Autoselect Command

Sequence section or more information.

9. Device ID must be read in three cycles.

10. If WP# protects highest address sector, data is 98h for factory

locked and 18h for not factory locked. If WP# protects lowest

address sector, data is 88h for factory locked and 08h for not

factor locked.

11. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

12. Total number of cycles in command sequence is determined by

number of bytes written to write buffer. Maximum number of

cycles in command sequence is 37, including "Program Buffer to

Flash" command.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

14. Unlock Bypass command is required prior to Unlock Bypass

Program command.

15. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

16. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Erase Suspend mode. Erase Suspend

command is valid only during a sector erase operation.

17. Erase Resume command is valid only during Erase Suspend

mode.

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