AT43USB353M datasheet(56/95 Pages) ATMEL

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AT43USB353M

3307B–USB–4/04

Port D Data Register – PORTD

Port D Data Direction Register – DDRD

Port D Input Pins Address – PIND

The Port D Input Pins address (PIND) is not a register, and this address enables access to the

physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and

when reading PIND, the logical values present on the pins are read.

PortD as General

Digital I/O

PDn, General I/O Pin: The DDDn bit in the DDRD register selects the direction of this pin. If

DDDn is set (one), PDn is con-figured as an output pin. If DDDn is cleared (zero), PDn is con-

figured as an input pin. If PORTDn is set (one) when the pin is configured as an input pin, the

MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTDn has to be

cleared (zero) or the pin has to configured as an output pin. The Port D pins are tri-stated

when a reset condition becomes active, even if the clock is not active.

Note:

n: 7, 6...0, pin number.

Bit

$12 ($32)

–

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

PORTD

Read/Write

R/W

Initial Value

Bit

210

$11 ($31)

–

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

DDRD

Read/Write

R/W

Initial Value

Bit

$10 ($30)

–

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

PIND

Read/Write

Initial Value

N/A

Table 26. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Comment

Input

Tri-state (Hi-Z)

Input

PDn will source current if ext. pulled low.

Output

Push-Pull Zero Output

Output

Push-Pull One Output

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