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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT43USB353M датащи(PDF) 19 Page - ATMEL Corporation |
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AT43USB353M датащи(HTML) 19 Page - ATMEL Corporation |
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19 / 95 page  19 AT43USB353M 3307B–USB–4/04 address $000 must be a JMP instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 6 shows the reset logic. Figure 6. Reset Logic Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. An internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V CC has reached the power-on threshold voltage, regardless of the VCC rise time. If the build-in start-up delay is sufficient, RESETN can be connected to V CC directly or via an external pull-up resistor. By holding the pin low for a period after V CC has been applied, the Power-on Reset period can be extended. External Reset An external reset is generated by a low-level on the RESETN pin. Reset pulses longer than 200 ns will generate a reset. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - V RST on its positive edge, the delay timer starts the MCU after the Time-out period t TOUT has expired. Figure 7. External Reset During Operation FSTRT Cntr Reset USB Reset OR POR Ckt Reset Ckt Watchdog Timer Divider 14-bit Cntr VCC RSTN 1 MHz Clock S R ON tTOUT VRST VCC RESET TIME-OUT INTERNAL RESET |
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