AT43USB353M datasheet(52/95 Pages) ATMEL

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AT43USB353M

3307B–USB–4/04

ADC Control and Status Register – ADCSR

•Bit 7

– ADEN: ADC Enable

Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned

off. Turning the ADC off while a conversion is in progress will terminate this conversion.

•Bit 6

– ADSC: ADC Start Conversion

In Single Conversion Mode, a logical “1” must be written to this bit to start each conversion. In

Free Running Mode, a logical “1” must be written to this bit to start the first conversion. The

first time ADSC has been written after the ADC has been enabled or if ADSC is written at the

same time as the ADC is enabled, an extended conversion will precede the initiated conver-

sion. This extended conversion performs initialization of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is com-

plete, it returns to zero. When a extended conversion precedes a real conversion, ADSC will

stay high until the real conversion completes. Writing a “0” to this bit has no effect.

•Bit 5

– ADFR: ADC Free Running Select

When this bit is set (one), the ADC operates in Free Running Mode. In this mode, the ADC

samples and updates the data registers continuously. Clearing this bit (zero) will terminate

Free Running Mode.

•Bit 4

– ADIF: ADC Interrupt Flag

This bit is set (one) when an ADC conversion completes and the data registers are updated.

The ADC Conversion Complete interrupt is executed if the ADIE bit and the I-bit in SREG are

set (one). ADIF is cleared by the hardware when executing the corresponding interrupt han-

dling vector. Alternatively, ADIF is cleared by writing a logical “1” to the flag. Beware that if

doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if

the SBI and CBI instructions are used.

•Bit 3

– ADIE: ADC Interrupt Enable

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete

interrupt is activated.

• Bits 2..0

– ADPS2..ADPS0: ADC Prescaler Select Bits

These bits determine the division factor between the 12 MHz system clock frequency and the

input clock to the ADC.

Bit

543

$07 ($27)

ADEN

ADSC

ADFR

ADIF

ADIE

ADPS2

ADPS1

ADPS0

ADCSR

Read/Write

R/W

Initial Value

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