AT43USB355_06 datasheet(61/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

The successive approximation circuitry requires an input clock frequency between 15 kHz and

1 MHz to achieve maximum resolution. If a resolution of 10 bits is required, the input clock fre-

quency to the ADC must be lower than 500 kHz to achieve a higher accuracy. See “ADC

Characteristics” on page 66 for more details. The ADC module contains a prescaler, which

divides the CK of 2 MHz clock input, to an acceptable ADC clock frequency.

The ADPS[0:2] bits in ADCSR are used to generate a proper ADC clock input frequency from

15.6 kHz to 1.0 MHz. The prescaler starts counting from the moment the ADC is switched on

by setting the ADEN bit in ADCSR. The prescaler keeps running for as long as the ADEN bit is

set and is continuously reset when ADEN is low.

When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the

following rising edge of the ADC clock cycle.

A normal conversion takes 12 ADC clock cycles. In certain situations, the ADC needs more

clock cycles for initialization and to minimize offset errors. Extended conversions take 25 ADC

clock cycles and occur as the first conversion after the ADC is switched on (ADEN in ADCSR

is set).

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a conversion.

When a conversion is complete, the result is written to the ADC data registers and ADIF is set.

In Single Conversion Mode, ADSC is cleared simultaneously. The software may then set

ADSC again and a new conversion will be initiated on the first rising ADC clock edge. In Free

Running Mode, a new conversion will be started immediately after the conversion completes,

while ADSC remains high. Using Free Running Mode and an ADC clock frequency of 1 MHz

gives the lowest conversion time with a maximum resolution, 12 µs, equivalent to 83 kSPS.

For a summary of conversion times, see Table 21.

Figure 24. ADC Timing Diagram, Extended Conversion (Single Conversion Mode)

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