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AT43USB355 датащи(PDF) 32 Page - ATMEL Corporation

номер детали AT43USB355
подробное описание детали  Full-speed USB Microcontroller with Embedded Hub, ADC and PWM
PDF  115 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT43USB355 датащи(HTML) 32 Page - ATMEL Corporation

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AT43USB355
2603G–USB–04/06
USB End-point
Interrupt Sources
An assertion or activation of one or more bits in the end-point's Control and Status Register
triggers the end-point interrupts. These triggers are different for control and non-control end-
points as described in the table below. Please refer to the Control and Status Register for
more information.
USB Interrupt Status Register – UISR
• Bit 7 – SOF INT: Start of Frame Interrupt
This bit is asserted after the USB hardware receives a valid SOF packet.
• Bit 6 – EOF2 INT: EOF2 Interrupt
This bit is asserted 10 clocks before the expected start of a frame.
• Bit 5 – Res: Reserved Bit
This bit is reserved and always reads as zero.
• Bit 4 – FEP3 INT: Function End-point 3 Interrupt
• Bit 3 – HEP0 INT: Hub End-point 0 Interrupt
• Bit 2 – FEP2 INT: Function End-point 2 Interrupt
• Bit 1 – FEP1 INT: Function End-point 1 Interrupt
• Bit 0 – FEP0 INT: Function End-point 0 Interrupt
The hub and function interrupt bits will be set by the hardware whenever the following bits in
the corresponding end-point's Control and Status Register are modified by the USB hardware:
1.
RX OUT Packet is set (control and OUT end-points)
2.
TX Packet Ready is cleared AND TX Complete is set (control and IN end-points)
3.
RX SETUP is set (control end-points only)
4.
TX Complete is set
Table 10. USB End-point Interrupt Sources
Bit
End-point type
RX_OUT_PACKET
CONTROL, OUT
TX_COMPLETE
CONTROL, IN
STALL_SENT
CONTROL, IN
RX_SETUP
CONTROL
Bit
7
6
5
4
3
2
1
0
$1FF7
SOF INT
EOF2 INT
FE3 INT
HEP0 INT
FE2 INT
FE1 INT
FE0 INT
UISR
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0



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