AT43USB355_06 datasheet(27/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

Timer/Counter Interrupt Mask Register – TIMSK

• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is

executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the

Timer/Counter Interrupt Flag Register (TIFR).

• Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is

set in the TIFR.

• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector

$005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is

set in the TIFR.

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

• Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vec-

tor $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1

bit is set in the TIFR.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is

executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT43USB355 and always reads zero.

Bit

210

$39 ($59)

TOIE1

OCIE1A

OCIE1NB

–

TICIE1

–

TOIE0

–

TIMSK

Read/Write

R/W

Initial Value

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