AT43USB355_06 datasheet(87/115 Pages) ATMEL

87 / 115 page

AT43USB355

2603G–USB–04/06

Hub End-point 0 Control and Acknowledge Register – HCAR0

Function End-point 0 Control and Acknowledge Register – FCAR0

•Bit 7 – DIR: Control transfer direction

It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB

hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard-

ware uses this bit to determine the status phase of a control transfer.

0 = control write or no data stage

1 = control read

•Bit 6 – DATA END

When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last

data packet in FIFO, or that the microcontroller has processed the last data packet it expects

from the Host. This bit is used by control end-points only together with bit 4 (TX Packet Ready)

to signal the USB hardware to go to the STATUS phase after the packet currently residing in

the FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the

microcontroller without clearing this bit.

•Bit 5 – FORCE STALL

This bit is set by the microcontroller to indicate a stalled end-point. The hardware will send a

STALL handshake as a response to the next IN or OUT token, or whenever there is a control

transfer without a Data Stage.

The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the fol-

lowing condition is encountered:

An unsupported request is received.

The host continues to ask for data after the data is exhausted.

The control transfer has no data stage.

•Bit 4 – TX PACKET READY: Transmit Packet Ready

When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a

packet of data. This bit is cleared by the hardware after the USB Host acknowledges the

packet. For ISO end-points, this bit is cleared unconditionally after the data is sent.

This bit is used for the following operations:

Control read transactions by a control end-point.

IN transactions with DATA1 PID to complete the status phase for a control end-point,

when this bit is zero but Data End set high (bit 4).

By a BULK IN or ISO IN or INT IN end-point.

The microcontroller should write into the FIFO only if this bit is cleared. After it has completed

writing the data, it should set this bit. This data can be of zero length.

Bit

Hub EP0

$1FA7

DIR

DATA

END

FORCE

STALL

PACKET

READY

STALL_

SENT_

ACK

RX_

SETUP_

ACK

RX_OUT_

PACKET_

ACK

TX_

COMPLETE_

ACK

HCAR0

Function

EP0 $1FDD

DIR

DATA

END

FORCE

STALL

PACKET

READY

STALL_

SENT_

ACK

RX_

SETUP_

ACK

RX_OUT_

PACKET_

ACK

TX_

COMPLETE_

ACK

FCAR0

Read/Write

R/W

Initial Value

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