SST25VF080B datasheet(12/33 Pages) MICROCHIP

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DS20005045D-page 12

SST25VF080B

4.4.7

4-KBYTE SECTOR ERASE

The Sector Erase instruction clears all bits in the

selected 4-Kbyte sector to FFH. A Sector Erase

instruction applied to a protected memory area will be

ignored. Prior to any Write operation, the Write Enable

(WREN) instruction must be executed. CE# must remain

active-low for the duration of any command sequence.

The Sector Erase instruction is initiated by executing

an 8-bit command, 20H, followed by address bits [A23-

A0]. Address bits [AMS-A12] (AMS = Most Significant

address) are used to determine the sector address

(SAX), remaining address bits can be VIL or VIH. CE#

must be driven high before the instruction is executed.

The user may poll the BUSY bit in the Software STA-

TUS Register or wait TSE for the completion of the inter-

nal self-timed Sector Erase cycle. See Figure 4-10 for

the Sector Erase sequence.

FIGURE 4-10:

SECTOR ERASE SEQUENCE

4.4.8

32-KBYTE AND 64-KBYTE BLOCK

ERASE

The 32-Kbyte Block Erase instruction clears all bits in

the selected 32 Kbyte block to FFH. A Block Erase

instruction applied to a protected memory area will be

ignored. The 64-Kbyte Block-Erase instruction clears

all bits in the selected 64 Kbyte block to FFH. A Block

Erase instruction applied to a protected memory area

will be ignored. Prior to any Write operation, the Write

Enable (WREN) instruction must be executed. CE# must

remain active-low for the duration of any command

sequence. The 32-Kbyte Block Erase instruction is ini-

tiated by executing an 8-bit command, 52H, followed by

address bits [A23-A0]. Address bits [AMS-A15]

(AMS = Most Significant Address) are used to deter-

mine block address (BAX), remaining address bits can

be VIL or VIH. CE# must be driven high before the

instruction is executed. The 64-Kbyte Block Erase

instruction is initiated by executing an 8-bit command

D8H, followed by address bits [A23-A0]. Address bits

[AMS-A15] are used to determine block address (BAX),

remaining address bits can be VIL or VIH. CE# must be

driven high before the instruction is executed. The user

may poll the BUSY bit in the Software STATUS Regis-

ter or wait TBE for the completion of the internal self-

timed 32-Kbyte Block Erase or 64-Kbyte Block Erase

cycles. See Figure 4-11 and Figure 4-12 for the 32-

Kbyte Block Erase and 64-Kbyte Block Erase

sequences.

FIGURE 4-11:

32-KBYTE BLOCK ERASE

SEQUENCE

FIGURE 4-12:

64-KBYTE BLOCK ERASE

SEQUENCE

CE#

SCK

ADD.

0 1 234 5 6 78

ADD.

15 16

23 24

MODE 0

MODE 3

CE#

SCK

ADDR

0 1 234 5 6 78

ADDR

MSB

15 16

23 24

MODE 0

MODE 3

MSB

CE#

SCK

ADDR

0 1 234 5 6 78

ADDR

MSB

15 16

23 24

MODE 0

MODE 3

MSB

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