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SST25VF080B датащи(PDF) 5 Page - Microchip Technology

номер детали SST25VF080B
подробное описание детали  8-Mbit SPI Serial Flash
PDF  33 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

SST25VF080B датащи(HTML) 5 Page - Microchip Technology

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2005-2020 Microchip Technology Inc.
DS20005045D-page 5
SST25VF080B
4.2
Write Protection
SST25VF080B provides software write protection. The
Write-Protect pin (WP#) enables or disables the lock-
down function of the STATUS Register. The Block Pro-
tection bits (BP3, BP2, BP1, BP0, and BPL) in the STA-
TUS register provide Write protection to the memory
array and the STATUS register. See Table 4-3 for the
Block Protection description.
4.2.1
WRITE PROTECTION PIN (WP#)
The Write-Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the STATUS Register.
When WP# is driven low, the execution of the Write
STATUS Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
4.3
STATUS Register
The software STATUS Register provides status on
whether the flash memory array is available for any
read or write operation, whether the device is Write
enabled, and the state of the Memory Write-protected.
During an internal erase or program operation, the
STATUS Register may be read only to determine the
completion of an operation in progress. Table 4-2
describes the function of each bit in the software STA-
TUS Register.
4.3.1
BUSY
The BUSY bit determines whether there is an internal
Erase or Program operation in progress. A ‘1’ for the
BUSY bit indicates the device is busy with an operation
in progress. A ‘0’ indicates the device is ready for the
next valid operation.
4.3.2
WRITE ENABLE LATCH (WEL)
The Write Enable Latch bit indicates the status of the
internal memory Write Enable Latch. If the Write
Enable Latch bit is set to ‘1’, it indicates the device is
Write enabled. If the bit is set to ‘0’ (reset), it indicates
the device is not write enabled and does not accept any
memory write (program/erase) commands. The Write
Enable Latch bit is automatically reset under the follow-
ing conditions:
• Power-up
• Write Disable (WRDI) instruction completion
• Byte Program instruction completion
• Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write STATUS Register instructions
TABLE 4-1:
CONDITIONS TO EXECUTE WRITE STATUS REGISTER (
WRSR) INSTRUCTIONS
WP#
BPL
Execute WRSR Instructions
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
TABLE 4-2:
SOFTWARE STATUS REGISTER
Bit
Name
Function
Default at
Power-up
Read/Write
0
BUSY
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
1
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See Table 4-3)
1
R/W
3
BP1
Indicate current level of block write protection (See Table 4-3)
1
R/W
4
BP2
Indicate current level of block write protection (See Table 4-3)
1
R/W
5
BP3
Indicate current level of block write protection (See Table 4-3)
0
R/W
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte Program mode
0
R
7
BPL
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are read/writable
0
R/W



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