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DS20005045D-page 3

SST25VF080B

2.0

PIN DESCRIPTION

FIGURE 2-1:

PIN ASSIGNMENTS

TABLE 2-1:

PIN DESCRIPTION

Symbol Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock input,

while output data is shifted out on the falling edge of the clock input.

SI

Serial Data Input

To transfer commands, addresses, or data serially into the device.

Inputs are latched on the rising edge of the serial clock.

SO

Serial Data Output To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

Outputs Flash busy status during AAI Programming when reconfigured as RY/BY#

pin. See

Section 4.4.5 “End of Write Detection” for details.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low for the

duration of any command sequence.

WP#

Write-Protect

The Write-Protect (WP#) pin is used to enable/disable BPL bit in the STATUS register.

HOLD# Hold

To temporarily stop serial communication with SPI flash memory without resetting the

device.

VDD

Power Supply

To provide power supply voltage:2.7V-3.6V for SST25VF080B.

VSS

Ground

Pin Assignment for 16-Ball XFBGA

2-IN

1-IN

D

C

B

A

2-OUT

1-OUT

SI

SCK HOLD# VDD

VSS WP#

SO

CE#

CE#

SO

WP#

VSS

VDD

HOLD#

SCK

SI

1

2

3

4

8

7

6

5

Pin Assignment for 8-Lead PDIP

Top View

Pin Assignment for 8-Lead SOIC

Pin Assignment for 8-Contact WSON

Top View

8

7

6

5

1

2

3

4

CE#

SO

WP#

V

SS

V

DD

HOLD#

SCK

SI

CE#

SO

WP#

VSS

VDD

HOLD#

SCK

SI

1

2

3

4

8

7

6

5

Top View

Top View

(Balls Facing Down)

Note 1: Outer bumps are connected to the inner bumps, but are not electrically tested. The outer bumps are used for mechanical support.

For footprint compatibility with other SST ZScale™ Packages, electrical connection to the eight inner bumps is required.