LTC2486IDE datasheet(32/36 Pages) LINER

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LTC2486

2486f

APPLICATIONS INFORMATION

Using the 2x speed mode of the LTC2486 alters the rejec-

tion characteristics around DC and multiples of fS. The

device bypasses the offset calibration in order to increase

the output rate. The resulting rejection plots are shown

in Figures 27 and 28. 1x type frequency rejection can be

achieved using the 2x mode by performing a running

average of the conversion results (see Figure 29).

Output Data Rate

When using its internal oscillator, the LTC2486 produces up

to 15 samples per second (sps) with a notch frequency of

60Hz. The actual output data rate depends upon the length

of the sleep and data output cycles which are controlled

by the user and can be made insigniﬁcantly short. When

operating with an external conversion clock (FO connected

to an external oscillator), the LTC2486 output data rate

can be increased. The duration of the conversion cycle is

41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves

as if the internal oscillator is used.

An increase in fEOSCoverthenominal307.2kHzwilltranslate

into a proportional increase in the maximum output data

rate (up to a maximum of 100sps). The increase in output

Figure 27. Input Normal Mode Rejection 2x Speed Mode

Figure 28. Input Normal Mode Rejection 2x Speed Mode

rate leads to degradation in offset, full-scale error, and ef-

fective resolution as well as a shift in frequency rejection.

When using the integrated temperature sensor, the internal

oscillator should be used or an external oscillator, fEOSC

= 307.2kHz maximum.

A change in fEOSC results in a proportional change in the

internal notch position. This leads to reduced differential

mode rejection of line frequencies. The common mode

rejection of line frequencies remains unchanged, thus fully

differential input signals with a high degree of symmetry

on both the IN+ and IN– pins will continue to reject line

frequency noise.

An increase in fEOSC also increases the effective dynamic

input and reference current. External RC networks will

continue to have zero differential input current, but the

time required for complete settling (580ns for fEOSC =

307.2kHz) is reduced, proportionally.

Once the external oscillator frequency is increased above

1MHz (a more than 3x increase in output rate) the effective-

ness of internal auto calibration circuits begins to degrade.

This results in larger offset errors, full scale errors, and

decreased resolution (see Figures 30 to 37).

INPUT SIGNAL FREQUENCY (fN)

2486 F27

–20

–40

–60

–80

–100

–120

2fN 3fN 4fN 5fN

6fN 7fN

8fN

INPUT SIGNAL FREQUENCY (fN)

2486 F28

–20

–40

–60

–80

–100

–120

250

248

252 254 256 258 260 262 264

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