LTC2486IDE datasheet(14/36 Pages) LINER

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LTC2486

2486f

APPLICATIONS INFORMATION

CONVERTER OPERATION

Converter Operation Cycle

The LTC2486 is a multi-channel, low power, delta-sigma,

analog-to-digital converter with an easy-to-use, 4-wire

interface and automatic differential input current cancella-

tion. Its operation is made up of four states (See Figure 2).

The converter operating cycle begins with the conversion,

followed by the sleep state, and ends with the data input/

output cycle. The 4-wire interface consists of serial data

output (SDO), serial clock (SCK), chip select (

⎯C⎯S) and

serial data input (SDI).The interface, timing, operation

cycle, and data output format is compatible with Linear’s

entire family of SPI

ΔΣ converters.

Initially, at power up, the LTC2486 performs a conversion.

Once the conversion is complete, the device enters the

sleep state. While in this sleep state, if

⎯C⎯S is HIGH, power

consumption is reduced by two orders of magnitude. The

part remains in the sleep state as long as

⎯C⎯S is HIGH. The

conversion result is held indeﬁnitely in a static shift register

while the part is in the sleep state.

Once

⎯C⎯S is pulled LOW, the device powers up, exits the

sleep state, and enters the data input/output state. If

⎯C⎯S

is brought HIGH before the ﬁrst rising edge of SCK, the

device returns to the sleep state and the power is reduced.

⎯C⎯S is brought HIGH after the ﬁrst rising edge of SCK, the

data output cycle is aborted and a new conversion cycle

begins. The data output corresponds to the conversion

just completed. This result is shifted out on the serial

data output pin (SDO) under the control of the serial

clock pin (SCK). Data is updated on the falling edge of

SCK allowing the user to reliably latch data on the rising

edge of SCK (See Figure 3). The conﬁguration data for

the next conversion is also loaded into the device at this

time. Data is loaded from the serial data input pin (SDI)

on each rising edge of SCK. The data input/output cycle

concludes once 24 bits are read out of the ADC or when

⎯C⎯S is brought HIGH. The device automatically initiates a

new conversion and the cycle repeats.

Through timing control of the

⎯C⎯SandSCKpins,theLTC2486

offers several ﬂexible modes of operation (internal or

external SCK and free-running conversion modes). These

various modes do not require programming and do not

disturb the cyclic operation described above. These modes

of operation are described in detail in the Serial Interface

Timing Modes section.

Ease of Use

The LTC2486 data output has no latency, ﬁlter settling

delay, or redundant data associated with the conversion

cycle. There is a one-to-one correspondence between the

conversion and the output data. Therefore, multiplexing

multiple analog inputs is straightforward. Each conver-

sion, immediately following a newly selected input or

mode, is valid and accurate to the full speciﬁcations of

the device.

The LTC2486 automatically performs offset and full scale

calibration every conversion cycle independent of the

input channel selected. This calibration is transparent to

the user and has no effect with the operation cycle de-

scribed above. The advantage of continuous calibration

is extreme stability of offset and full-scale readings with

respect to time, supply voltage variation, input channel,

and temperature drift.

Figure 2. LTC2486 State Transition Diagram

CONVERT

SLEEP

CHANNEL SELECT

CONFIGURATION SELECT

DATA OUTPUT

POWER UP

IN+= CH0, IN–= CH1

50/60Hz, GAIN = 1, 1X

2486 F02

CS = LOW

AND

SCK

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