LTC2486IDE datasheet(17/36 Pages) LINER

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LTC2486

2486f

APPLICATIONS INFORMATION

+FS. If both Bit 21 and Bit 20 are LOW, the differential

input voltage is below –FS. The function of these bits is

summarized in Table 1.

Table 1. LTC2486 Status Bits

Input Range

Bit 23

⎯E⎯O⎯C

Bit 22

DMY

Bit 21

SIG

Bit 20

MSB

VIN ≥ 0.5 • VREF/Gain

0011

0V ≤ VIN < 0.5 • VREF/Gain

0010

–0.5 • VREF/Gain ≤ VIN < 0V

0001

VIN < –0.5 • VREF/Gain

0000

Bits 20 to 4 are the 16-bit plus sign conversion result

MSB ﬁrst.

Bit 4 is the least signiﬁcant bit (LSB16).

Bits 3 to 0 are always LOW.

Data is shifted out of the SDO pin under control of the

serial clock (SCK) (see Figure 3). Whenever

⎯C⎯S is HIGH,

SDO remains high impedance and SCK is ignored.

In order to shift the conversion result out of the device,

⎯C⎯S must ﬁrst be driven LOW. ⎯E⎯O⎯C is seen at the SDO pin

of the device once

⎯C⎯S is pulled LOW. ⎯E⎯O⎯C changes in real

time as a function of the internal oscillator or the clock

applied to the fO pin from HIGH to LOW at the completion

of a conversion. This signal may be used as an interrupt for

an external microcontroller. Bit 23 (

⎯E⎯O⎯C) can be captured

on the ﬁrst rising edge of SCK. Bit 22 is shifted out of the

device on the ﬁrst falling edge of SCK. The ﬁnal data bit

(Bit 0) is shifted out on the on the falling edge of the 23rd

SCK and may be latched on the rising edge of the 24th SCK

pulse. On the falling edge of the 24th SCK pulse, SDO goes

HIGH indicating the initiation of a new conversion cycle.

This bit serves as

⎯E⎯O⎯C (Bit 23) for the next conversion

cycle. Table 2 summarizes the output data format.

As long as the voltage on the IN+ and IN– pins remains

between –0.3V and VCC + 0.3V (absolute maximum op-

erating range) a conversion result is generated for any

differential input voltage VIN from –FS = –0.5 • VREF/Gain

to +FS = 0.5 • VREF/Gain. For differential input voltages

greater than +FS, the conversion result is clamped to the

value corresponding to +FS + 1LSB. For differential input

voltages below –FS, the conversion result is clamped to

the value –FS – 1LSB.

INPUT DATA FORMAT

The LTC2486 serial input word is 16 bits long and contains

two distinct sets of data. The ﬁrst set (SGL, ODD, A2,

A1, A0) is used to select the input channel. The second

set of data (IM, FA, FB, SPD, GS2, GS1, GS0) is used

to select the frequency rejection, speed mode (1x, 2x),

temperature measurement, and gain.

After power up, the device initiates an internal reset cycle

which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =

CH1), the frequency rejection to simultaneous 50Hz/60Hz,

1x output rate (auto-calibration enabled), and gain = 1. The

ﬁrst conversion automatically begins at power up using this

default conﬁguration. Once the conversion is complete, a

new word may be written into the device.

Figure 3. Channel Selection, Conﬁguration Selection and Data Output Timing

EOC

SCK

(EXTERNAL)

SDI

SDO

2486 F03

CONVERSION

SLEEP

DATA INPUT/OUTPUT

MSB

BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11

SIG

BIT 21

“0”

BIT 22

BIT 23

SGL

EN2

SPD

GS2

GS1

GS0

ODD

BIT 10

BIT 9

BIT 0

141516

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