LTC2486IDE datasheet(22/36 Pages) LINER

22 / 36 page

LTC2486

2486f

The external serial clock mode is selected during the power-

up sequence and on each falling edge of

⎯C⎯S. In order to

enter and remain in the external SCK mode of operation,

SCK must be driven LOW both at power up and on each

⎯C⎯S falling edge. If SCK is HIGH on the falling edge of ⎯C⎯S,

the device will switch to the internal SCK mode.

The serial data output pin (SDO) is Hi-Z as long as

⎯C⎯S is

HIGH. At any time during the conversion cycle,

⎯C⎯S may be

pulled LOW in order to monitor the state of the converter.

While

⎯C⎯S is LOW, ⎯E⎯O⎯C is output to the SDO pin.

⎯E⎯O⎯C = 1 while a conversion is in progress and ⎯E⎯O⎯C = 0 if

the conversion is complete and the device is in the sleep

state. Independent of

⎯C⎯S, the device automatically enters

the sleep state once the conversion is complete; however,

in order to reduce the power,

⎯C⎯S must be HIGH.

When the device is in the sleep state, its conversion result

is held in an internal static shift register. The device remains

in the sleep state until the ﬁrst rising edge of SCK is seen

while

⎯C⎯S is LOW. The input data is then shifted in via the

SDI pin on each rising edge of SCK (including the ﬁrst rising

edge). The channel selection and converter conﬁguration

mode will be used for the following conversion cycle. If

the input channel or converter conﬁguration is changed

during this I/O cycle, the new settings take effect on the

conversion cycle following the data input/output cycle.

The output data is shifted out the SDO pin on each falling

edge of SCK. This enables external circuitry to latch the

output on the rising edge of SCK.

⎯E⎯O⎯C can be latched on

the ﬁrst rising edge of SCK and the last bit of the conver-

sion result can be latched on the 24th rising edge of SCK.

On the 24th falling edge of SCK, the device begins a new

conversion and SDO goes HIGH (

⎯E⎯O⎯C = 1) indicating a

conversion is in progress.

At the conclusion of the data cycle,

⎯C⎯S may remain LOW

and

⎯E⎯O⎯C monitored as an end-of-conversion interrupt.

Typically,

⎯C⎯S remains LOW during the data output/input

state. However, the data output state may be aborted by

pulling

⎯C⎯S HIGH any time between the 1st falling edge

and the 24th falling edge of SCK (see Figure 7). On the

rising edge of

⎯C⎯S, the device aborts the data output state

and immediately initiates a new conversion. In order to

program a new input channel, 8 SCK clock pulses are

required. If the data output sequence is aborted prior to

the 8th falling edge of SCK, the new input data is ignored

and the previously selected input channel remains valid.

If the rising edge of

⎯C⎯S occurs after the 8th falling edge of

SCK, the new input channel is loaded and valid for the next

conversion cycle. If

⎯C⎯S goes high between the 8th falling

edge and the 16th falling edge of SCK, the new channel

is still loaded, but the converter conﬁguration remains

unchanged. In order to program both the input channel

and converter conﬁguration,

⎯C⎯S must go high after the

16th falling edge of SCK (at this point all data has been

shifted into the device).

External Serial Clock, 3-Wire I/O

This timing mode uses a 3-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal (see Figure 8).

⎯C⎯S is permanently tied to ground, simplifying the user

interface or isolation barrier.

The external serial clock mode is selected at the end of

the power-on reset (POR) cycle. The POR cycle typically

concludes 4ms after VCC exceeds 2V. The level applied to

SCK at this time determines if SCK is internally generated

or externally applied. In order to enter the external SCK

mode, SCK must be driven LOW prior to the end of the

POR cycle.

Since

⎯C⎯S is tied LOW, the end-of-conversion (⎯E⎯O⎯C) can be

continuously monitored at the SDO pin during the convert

and sleep states.

⎯E⎯O⎯C may be used as an interrupt to an

external controller.

⎯E⎯O⎯C = 1 while the conversion is in

progress and

⎯E⎯O⎯C = 0 once the conversion is complete.

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