LTC2486IDE datasheet(24/36 Pages) LINER

24 / 36 page

LTC2486

2486f

APPLICATIONS INFORMATION

On the falling edge of

⎯E⎯O⎯C, the conversion result is load-

ing into an internal static shift register. The output data

can now be shifted out the SDO pin under control of the

externally applied SCK signal. Data is updated on the fall-

ing edge of SCK. The input data is shifted into the device

through the SDI pin on the rising edge of SCK. On the

24th falling edge of SCK, SDO goes HIGH, indicating a

new conversion has begun. This data now serves as

⎯E⎯O⎯C

for the next conversion.

Internal Serial Clock, Single Cycle Operation

This timing mode uses the internal serial clock to shift out

the conversion result and

⎯C⎯S to monitor and control the

state of the conversion cycle (see Figure 9).

In order to select the internal serial clock timing mode,

the serial clock pin (SCK) must be ﬂoating or pulled HIGH

before the conclusion of the POR cycle and prior to each

falling edge of

⎯C⎯S.Aninternalweakpull-upresistorisactive

on the SCK pin during the falling edge of

⎯C⎯S; therefore,

the internal SCK mode is automatically selected if SCK is

not externally driven.

The serial data output pin (SDO) is Hi-Z as long as

⎯C⎯S is

HIGH. At any time during the conversion cycle,

⎯C⎯S may be

pulled low in order to monitor the state of the converter.

Once

⎯C⎯S is pulled LOW, SCK goes LOW and ⎯E⎯O⎯C is output

to the SDO pin.

⎯E⎯O⎯C = 1 while the conversion is in progress

and

⎯E⎯O⎯C = 0 if the device is in the sleep state.

When testing

⎯E⎯O⎯C, if the conversion is complete (⎯E⎯O⎯C =

0), the device will exit sleep state. In order to return to the

sleep state and reduce the power consumption,

⎯C⎯Smustbe

pulled HIGH before the device pulls SCK HIGH. When the

device is using its own internal oscillator (FO is tied LOW),

the ﬁrst rising edge of SCK occurs 12µs (tEOCTEST = 12µs)

after the falling edge of

⎯C⎯S. If F

O is driven by an external

oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.

⎯C⎯S remains LOW longer than t

EOCTEST, the ﬁrst rising

edge of SCK will occur and the conversion result is shifted

out the SDO pin on the falling edge of SCK. The serial

input word (SDI) is shifted into the device on the rising

edge of SCK.

After the 24th rising edge of SCK a new conversion au-

tomatically begins. SDO goes HIGH (

⎯E⎯O⎯C = 1) and SCK

Figure 9. Internal Serial Clock, Single Cycle Operation

Hi-Z

2486 F09

SCK

(INTERNAL)

SDI

SDO

CONVERSION

SLEEP

DATA INPUT/OUTPUT

VCC

SCK

SDI

GND

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

LTC2486

4-WIRE

SPI INTERFACE

EOC

BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13

BIT 12 BIT 11

BIT 21

BIT 22

BIT 23

BIT 10

BIT 9

BIT 0

121314

1516

SGL

EN2

SPD

GS2

GS1

GS0

ODD

DON'T CARE

MSB

SIG

“0”

OPTIONAL

10k

VCC

<tEOCTEST

REF+

REF–

CH0

CH1

CH2

CH3

COM

2.7V TO 5.5V

0.1

µF

SDO

CONVERSION

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