LXT386LE datasheet(49/78 Pages) INTEL

номер детали	LXT386LE

подробное описание детали	QUAD T1/E1/J1 Transceiver

PDF	78 Pages

Scroll/Zoom	100%

производитель	INTEL [Intel Corporation]

домашняя страница	http://www.intel.com

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49 / 78 page

QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

LOOP0

I/O

PDO0

LOOP1

I/O

PADI1

LOOP1

I/O

PDO1

LOOP2

I/O

PADI2

LOOP2

I/O

PDO2

LOOP3

I/O

PADI3

LOOP3

I/O

PDO3

LOOP4

I/O

PADI4

LOOP4

I/O

PDO4

LOOP5

I/O

PADI5

LOOP5

I/O

PDO5

LOOP6

I/O

PADI6

LOOP6

I/O

PDO6

LOOP7

I/O

PADI7

N/A

PDOENB

PDOENB controls the LOOP0 through LOOP7 pins.

Setting PDOENB to “0” configures the pins as outputs. The output value

to the pin is set in PDO[0..7].

Setting PDOENB to “1” tristates all the pins. The input value to the pins

can be read in PADD[0..7].

LOOP7

I/O

PDO7

ICSB

MUX

RESET

IRSTB

MOT/INTL

IMB

R/W

RDB

IWRB

TCLK1

TPOS1

TNEG1

RCLK1

RPOS1

N/A

HIZ1

HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to “0”

enables output on the pins. Setting HIZ1 to “1” tristates the pins.

RNEG1

LOS1

TCLK0

TPOS0

TNEG0

RCLK0

Example 1. Boundary Scan Register (BSR) (Continued)

Bit #

Signal

I/O

Type

Bit

Symbol

Comments

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