LXT386LE datasheet(4/78 Pages) INTEL

4 / 78 page

LXT386 — QUAD T1/E1/J1 Transceiver

Datasheet

5.3

TAP Controller..................................................................................................... 45

5.4

JTAG Register Description.................................................................................. 47

5.4.1

Boundary Scan Register (BSR).............................................................. 48

5.5

Device Identification Register (IDR) .................................................................... 50

5.5.1

Bypass Register (BYR) .......................................................................... 50

5.5.2

Analog Port Scan Register (ASR) .......................................................... 50

5.5.3

Instruction Register (IR) ......................................................................... 51

6.0

Test Specifications.................................................................................................. 53

6.1

Recommendations and Specifications ................................................................ 75

7.0

Mechanical Specifications ................................................................................... 76

Figures

LXT386 Block Diagram ......................................................................................... 7

LXT386 Detailed Block Diagram ........................................................................... 8

LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Pack-

age Markings......................................................................................................... 9

LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments........................... 10

Pullup Resistor to RESET ................................................................................... 23

50% AMI Encoding.............................................................................................. 26

External Transmit/Receive Line Circuitry ............................................................ 29

Jitter Attenuator Loop.......................................................................................... 31

Analog Loopback ................................................................................................ 31

Digital Loopback.................................................................................................. 32

Remote Loopback ............................................................................................... 32

TAOS Data Path ................................................................................................. 33

TAOS with Analog Loopback .............................................................................. 33

Serial Host Mode Timing ..................................................................................... 37

LXT386 JTAG Architecture ................................................................................. 45

JTAG State Diagram ........................................................................................... 47

Analog Test Port Application ............................................................................... 52

Transmit Clock Timing Diagram .......................................................................... 59

Receive Clock Timing Diagram ........................................................................... 60

JTAG Timing ....................................................................................................... 61

Non-Multiplexed Intel Mode Read Timing ........................................................... 62

Multiplexed Intel Read Timing ............................................................................. 63

Non-Multiplexed Intel Mode Write Timing ........................................................... 64

Multiplexed Intel Mode Write Timing ................................................................... 65

Non-Multiplexed Motorola Mode Read Timing .................................................... 66

Multiplexed Motorola Mode Read Timing............................................................ 67

Non-Multiplexed Motorola Mode Write Timing .................................................... 68

Multiplexed Motorola Mode Write Timin .............................................................. 69

Serial Input Timing .............................................................................................. 70

Serial Output Timing ........................................................................................... 70

E1, G.703 Mask Templates................................................................................. 71

T1, T1.102 Mask Templates ............................................................................... 72

LXT386 Jitter Tolerance Performance ................................................................ 73

Jitter Transfer Performance ................................................................................ 74

LXT386LE датащи(PDF) 4 Page - Intel Corporation

LXT386LE датащи(HTML) 4 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL