LXT386LE datasheet(15/78 Pages) INTEL

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QUAD T1/E1/J1 Transceiver — LXT386

Datasheet

RCLK0

Receive Clock.

Normal Mode:

This pin provides the recovered clock from the signal received at RTIP and

RRING. Under LOS conditions there is a transition from RCLK signal

(derived from the recovered data) to MCLK signal at the RCLK output.

Data Recovery Mode:

If MCLK is High, the clock recovery circuit is disabled and RPOS and

RNEG are internally connected to an EXOR that is fed to the RCLK output

for external clock recovery applications.

RCLK will be in high impedance state if the MCLK pin is Low.

RPOS0/

RDATA0

Receive Positive.

Receive Data.

Receive Negative Data.

Bipolar Violation Detect.

Bipolar Mode:

In clock recovery mode these pins act as active high bipolar non return to

zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to

receipt of a positive pulse on RTIP/RRING. A High signal on RNEG

corresponds to receipt of a negative pulse on RTIP/RRING. These signals

are valid on the falling or rising edges of RCLK depending on the CLKE

input.

In Data recovery Mode these pins act as RZ data receiver outputs. The

output polarity is selectable with CLKE (Active High output polarity when

CLKE is High and Active Low Polarity when CLKE is Low).

RPOS and RNEG will go to the high impedance state when the MCLK pin

is Low.

Unipolar Mode:

In uni-polar mode, the LXT386 asserts BPV High if any in-service Line

Code Violation is detected. RDATA acts as the receive data output.

Hardware Mode: During a LOS condition, RPOS and RNEG will remain

active.

Host Mode: RPOS and RNEG will either remain active or insert AIS into

the receive path. Selection is determined by the RAISEN bit in the GCR

RNEG0/

BPV0

LOS0

Loss of Signal. LOS goes High to indicate a loss of signal, i.e. when the

incoming signal has no transitions for a specified time interval. The LOS

condition is cleared and the output pin returns to Low when the incoming signal

has sufficient number of transitions in a specified time interval. See “Loss of

Signal Detector” on page 24.

MUX

Multiplexed/Non-Multiplexed Select.

When Low the parallel host interface operates in non-multiplexed mode.

When High the parallel host interface operates in multiplexed mode. In

hardware mode tie this unused input low.

N4, P4

TVCC0

Transmit Driver Power Supply. Power supply pin for the port 0 output

driver. TVCC pins can be connected to either a 3.3V or 5V power supply.

Refer to the Transmitter description.

Table 1.

Pin Assignments and Signal Descriptions (Continued)

Ball #

PBGA

Pin #

LQFP

Symbol

I/O1

Description

1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;

N.C.: Not Connected.

2. N/C means “Not Connected”

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