CS5535 datasheet(279/555 Pages) NSC

279 / 555 page

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USB Register Descriptions (Continued)

5.5.4.3

Host Controller Command Status (USBC_HcCommandStatus)

5.5.4.4

Host Controller Interrupt Status (USBC_HcInterruptStatus)

All bits are set by the hardware and cleared by software.

USB Memory Offset

08h

Type

HCD:

HC:

R/W

Reset Value

00000000h

USBC_HcCommandStatus Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

7654321

RSVD

USBC_HcCommandStatus Bit Descriptions

Bit

Name

HCD

Description

31:18

RSVD

R/W

Reserved. Read/write 0s.

17:16

Schedule

OverrunCount

R/W

Schedule Overrun Count. This field increments every time the

SchedulingOverrun bit in HcInterruptStatus is set. The count

wraps from 11 to 00.

15:4

RSVD

R/W

Reserved. Read/write 0s.

Ownership

ChangeRequest

R/W

Ownership Change Request. When set by software, this bit

sets the OwnershipChange field in HcInterruptStatus. The bit is

cleared by software. This field always reads back as 0.

BulkListFilled

R/W

Bulk List Filled. Set to indicate there is an active ED on the Bulk

List. The bit may be set by either software or the HC and cleared

by the HC each time it begins processing the head of the Bulk

List.

ControlListFilled

R/W

Control List Filled. Set to indicate there is an active ED on the

Control List. It may be set by either software or the HC and

cleared by the HC each time it begins processing the head of the

Control List.

HostControllerRe-

set

R/W

Host Controller Reset. This bit is set to initiate a software reset.

This bit is cleared by the HC upon completion of the reset opera-

tion. This field always reads back as 0.

USB Memory Offset

0Ch

Type

HCD:

HC:

R/W

Reset Value

00000000h

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