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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5535 датащи(PDF) 276 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 276 Page - National Semiconductor (TI) |
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276 / 555 page  www.national.com 276 Revision 0.8 USB Register Descriptions (Continued) 5.5.3.15 Maximum Latency (USBC_PCI_MAX_LTNCY) 5.5.3.16 ASIC Test Mode Enable (USBC_PCI_ASIC_TEST) 5.5.3.17 ASIC Operational Mode Enable (USBC_PCI_ASIC_MODE) Index 3Fh Type R/W Reset Value 50h USBC_PCI_MAX_LTNCY Register Map 76 54 32 10 MAX_LTNCY USBC_PCI_MAX_LTNCY Bit Descriptions Bit Name Description 7:0 MAX_LTNCY Maximum Latency. This register specifies the desired settings for how often the USB needs access to the PCI bus assuming a clock rate of 33 MHz. The value specifies a period of time in units of 1/4 microsecond. Index 40h Type R/W Reset Value 000F0000h USBC_PCI_ASIC_TEST Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7654321 0 RSVD USBC_PCI_ASIC_TEST Bit Descriptions Bit Name Description 31:0 RSVD Reserved. These bits are reserved for internal testing only. These bits should not be written to. Index 44h Type R/W Reset Value 0000h USBC_PCI_ASIC_MODE Register Map 15 14 13 12 11 10 9876 5432 10 RSVD RSVD USBC_PCI_ASIC_MODE Bit Descriptions Bit Reset Description 15:9 RSVD Reserved. Write 0s; reads undefined. |
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