CS5535 datasheet(282/555 Pages) NSC

282 / 555 page

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282

Revision 0.8

USB Register Descriptions (Continued)

5.5.4.6

Host Controller Interrupt Disable (USBC_HcInterruptDisable)

Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged.

USB Memory Offset

14h

Type

HCD:

HC:

R/W

Reset Value

00000000h

USBC_HcInterruptDisable Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

7654321

RSVD

USBC_HcInterruptDisable Bit Descriptions

Bit

Name

HCD

Description

MasterInterrupt

Enable

R/W

Master Interrupt Disable. Global interrupt disable. A write of 1

disables all interrupts.

Ownership

ChangeEnable

R/W

Ownership Change Disable.

0: Ignore.

1: Disable interrupt generation due to Ownership Change.

29:7

RSVD

R/W

Reserved. Read/write 0s.

RootHubStatus

ChangeEnable

R/W

Root Hub Status Change Disable.

0: Ignore.

1: Disable interrupt generation due to Root Hub Status Change.

FrameNumber

OverflowEnable

R/W

Frame Number Overflow Disable.

0: Ignore.

1: Disable interrupt generation due to Frame Number Overflow.

Unrecoverable

ErrorEnable

R/W

Unrecoverable Error Disable. This event is not implemented. All

writes to this bit will be ignored.

Resume

DetectedEnable

R/W

Resume Detected Disable.

0: Ignore.

1: Disable interrupt generation due to Resume Detected.

2StartOfFrame

Enable

R/W

Start Of Frame Disable.

0: Ignore.

1: Disable interrupt generation due to Start of Frame.

WritebackDone

HeadEnable

R/W

Writeback Done Head Disable.

0: Ignore.

1: Disable interrupt generation due to Writeback Done Head.

Scheduling

OverrunEnable

R/W

Scheduling Overrun Disable.

0: Ignore.

1: Disable interrupt generation due to Scheduling Overrun.

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