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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5535 датащи(PDF) 274 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 274 Page - National Semiconductor (TI) |
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274 / 555 page  www.national.com 274 Revision 0.8 USB Register Descriptions (Continued) 5.5.3.10 BIST (USBC_PCI_BIST) 5.5.3.11 Base Address Register (USBC_PCI_BAR) This BAR sets the base address of the memory mapped USB controller registers. Bits [11:0] are read only (0000 0000 0000), indicating a 4 kB memory address range. Refer to Section 5.5.4 "Host Controller Native Registers" on page 277 for the USB controller register bit formats and reset values. USBC_PCI_HEADER Bit Descriptions Bit Name Description 7:0 PCI_HEADER PCI Header Type. This register identifies the type of the predefined header in the con- figuration space. Since the USB is a single function device and not a PCI-to-PCI bridge, this byte should be read as 00h. Index 0Fh Type RO Reset Value 00h USBC_PCI_BIST Register Map 76 54 32 10 PCI_BIST USBC_PCI_BIST Bit Descriptions Bit Name Description 7:0 PCI_BIST PCI BIST. This register identifies the control and status of Built In Self Test. The USB does not implement BIST, so this register is read only. Index 10h Type R/W Reset Value 00000000h USBC_PCI_BAR Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7654321 0 BASE_ADDR ADDR_RNG WIDTH USBC_PCI_BAR Bit Descriptions Bit Name Description 31:12 BASE_ADDR Base Address. POST writes the value of the memory base address to this register. 11:4 ADDR_RNG Address Range (Always 0.) Indicates a 4k byte address range is requested. 3PREFETCH Prefetch (Always 0). Indicates there is no support for prefetchable memory. 2:1 WIDTH Width (Always 0). Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space. 0MEM Memory (Always 0). Indicates that the operational registers are mapped into memory space. |
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