CS5535 datasheet(272/555 Pages) NSC

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272

Revision 0.8

USB Register Descriptions (Continued)

5.5.3.5

Device Revision Identification (USBC_PCI_DEVREVID)

5.5.3.6

PCI Class Code (USBC_PCI_CLASS)

USBC_PCI_STS Bit Descriptions

Bit

Name

Description

PAR_ERR

Detected Parity Error. This bit is set whenever the USB detects a parity error, even if

the Parity Error (response) detection enable bit (Index 04h[6]) is disabled. Write 1 to

clear.

SERR_ERR

SERR# Status. This bit is set whenever the USB detects a PCI address error. Write 1

to clear.

RCVD_MSTR_

ABT_STS

Received Master Abort Status. This bit is set when the USB, acting as a PCI master,

aborts a PCI bus memory cycle. Write 1 to clear.

RCVD_TRGT_

ABT_STS

Received Target Abort Status. This bit is set when a USB generated PCI cycle (USB

is the PCI master) is aborted by a PCI target. Write 1 to clear.

SIG_TRGT_

ABT_STS

Signaled Target Abort Status. This bit is set whenever the USB signals a target abort.

Write 1 to clear.

10:9

DEVSEL_TIME

DEVSEL# Timing (Read Only). These bits indicate the DEVSEL# timing when per-

forming a positive decode. Since DEVSEL# is asserted to meet the medium timing,

these bits are encoded as 01.

DATA_PAR

Data Parity Reported. Set to 1 if the Parity Error bit (Command Register bit 6) is set,

and USB detects PERR# asserted while acting as PCI master (whether PERR# was

driven by USB or not).

7FB2B

Fast Back-to-Back Capable (Read Only). USB does support fast back-to-back trans-

actions when the transactions are not to the same agent. This bit is always 1.

6:0

RSVD

Reserved. Set to 0.

Index

08h

Type

Reset Value

06h

USBC_PCI_DEVREVID Register Map

DEV_REV_ID

USBC_PCI_DEVREVID Bit Descriptions

Bit

Name

Description

7:0

DEV_REV_ID

Device Revision ID.

Index

09h

Type

Reset Value

0C0310h

USBC_PCI_CLASS Register Map

PCI_CLASS

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