CS5535 datasheet(196/555 Pages) NSC

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196

Revision 0.8

GLIU Register Descriptions (Continued)

5.1.3

GLIU Specific MSRs

5.1.3.1

Coherency (GLIU_COH)

5.1.3.2

Port Active Enable (GLIU_PAE)

MSR Address

51010080h

Type

R/W

Reset Value

00000000_00000000h

GLIU_COH Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

987654

3210

RSVD

COHP

GLIU_COH Bit Descriptions

Bit

Name

Description

63:3

RSVD

Reserved. Write as read.

2:0

COHP

Coherent Device Port. The port that coherent snoops are routed to. If the coherent device

is on the other side of a bridge, the COHP points to the bridge.

000: Port 0 (GLIU)

100: Port 4 (DD)

001: Port 1 (GLPCI_SB)

101: Port 5 (ACC)

010: Port 2 (USBC2)

110: Port 6 (USBC1)

011: Port 3 (ATAC)

111: Port 7 (GLCP)

MSR Address

51010081h

Type

R/W

Reset Value

00000000_0000FFFFh

GLIU_PAE Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

PAE0

PAE7

PAE6

PAE5

PAE4

PAE3

PAE2

PAE1

GLIU_PAE Bit Descriptions

Bit

Name

Description

63:16

RSVD

Reserved. Write as read.

15:14

PAE0

Port Active Enable for Port 0 (GLIU).

00: OFF - Master transactions are disabled.

01: LOW - Master transactions limited to one outstanding transaction.

10: Reserved.

11: ON - Master transactions enabled with no limitations.

13:12

PAE7

Port Active Enable for Port 7 (GLCP).See bits [15:14] for decode.

11:10

PAE6

Port Active Enable for Port 6 (USBC1). See bits [15:14] for decode.

9:8

PAE5

Port Active Enable for Port 5 (ACC). See bits [15:14] for decode.

7:6

PAE4

Port Active Enable for Port 4 (DD). See bits [15:14] for decode.

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