CS5535 datasheet(198/555 Pages) NSC

198 / 555 page

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198

Revision 0.8

GLIU Register Descriptions (Continued)

5.1.3.5

Asynchronous Error (GLIU_AERR)

ERR is a condensed version of the port (asynchronous) ERR signals. The EN bits ([15:8]) can be used to prevent a device

from issuing an ERR. A write of 1 to the EN bit disables the device’s ERR. The FLAG bits ([7:0]) are status bits. If high, an

ERR was generated due to the associated device. (See Section 3.1.4 "ASMI and Error" on page 51 for further details.)

GLIU_ASMI Bit Descriptions

Bit

Name

Description

63:16

RSVD

Reserved.

P7_ASMI_EN

Port 7 (GLCP) Asynchronous SMI Enable.

P6_ASMI_EN

Port 6 (USBC1) Asynchronous SMI Enable.

P5_ASMI_EN

Port 5 (ACC) Asynchronous SMI Enable.

P4_ASMI_EN

Port 4 (DD) Asynchronous SMI Enable.

P3_ASMI_EN

Port 3 (ATAC) Asynchronous SMI Enable.

P2_ASMI_EN

Port 2 (USBC2) Asynchronous SMI Enable.

P1_ASMI_EN

Port 1 (GLPCI_SB) Asynchronous SMI Enable.

P0_ASMI_EN

Port 0 (GLIU) Asynchronous SMI Enable.

P7_ASMI_FLAG (RO)

Port 7 (GLCP) Asynchronous SMI Flag (Read Only).

P6_ASMI_FLAG (RO)

Port 6 (USBC1) Asynchronous SMI Flag (Read Only).

P5_ASMI_FLAG (RO)

Port 5 (ACC) Asynchronous SMI Flag (Read Only).

P4_ASMI_FLAG (RO)

Port 4 (DD) Asynchronous SMI Flag (Read Only).

P3_ASMI_FLAG (RO)

Port 3 (ATAC) Asynchronous SMI Flag (Read Only).

P2_ASMI_FLAG (RO)

Port 2 (USBC2) Asynchronous SMI Flag (Read Only).

P1_ASMI_FLAG (RO)

Port 1 (GLPCI_SB) Asynchronous SMI Flag (Read Only).

P0_ASMI_FLAG (RO)

Port 0 (GLIU) Asynchronous SMI Flag (Read Only).

MSR Address

51010084h

Type

R/W

Reset Value

00000000_00000000h

GLIU_AERR Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

7654321

RSVD

GLIU_AERR Bit Descriptions

Bit

Name

Description

63:16

RSVD

Reserved.

P7_AERR_EN

Port 7 (GLCP) Asynchronous Error Enable.

P6_AERR_EN

Port 6 (USBC1) Asynchronous Error Enable.

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