CS5535 datasheet(197/555 Pages) NSC

197 / 555 page

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GLIU Register Descriptions (Continued)

5.1.3.3

Arbitration (GLIU_ARB)

5.1.3.4

Asynchronous SMI (GLIU_ASMI)

ASMI is a condensed version of the Port ASMI signals. The EN bits ([15:8]) can be used to prevent a device from issuing an

ASMI. A write of 1 to the EN bit disables the device’s ASMI. The FLAG bits ([7:0]) are status bits. If high, an ASMI was gen-

erated due to the associated device. (See Section 3.1.4 "ASMI and Error" on page 51 for further details.)

5:4

PAE3

Port Active Enable for Port 3 (ATAC). See bits [15:14] for decode.

3:2

PAE2

Port Active Enable for Port 2 (USBC2). See bits [15:14] for decode.

1:0

PAE1

Port Active Enable for Port 1 (GLPCI_SB).

MSR Address

51010082h

Type

R/W

Reset Value

00000000_00000000h

GLIU_ARB Register

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

987654

3210

RSVD

GLIU_ARB Bit Descriptions

Bit

Name

Description

RSVD

Reserved. Write as read.

PIPE_DIS

Pipelined Arbitration Disabled.

0: Pipelined arbitration enabled and the GLIU is not limited to one outstanding transaction.

1: Limit the entire GLIU to one outstanding transaction.

61:0

RSVD

Reserved. Write as read.

MSR Address

51010083h

Type

R/W

Reset Value

00000000_00000000h

GLIU_ASMI Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9876

543

210

RSVD

GLIU_PAE Bit Descriptions (Continued)

Bit

Name

Description

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